From patchwork Fri Aug 26 09:59:18 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 3719 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B177B23F41 for ; Fri, 26 Aug 2011 09:59:26 +0000 (UTC) Received: from mail-gw0-f52.google.com (mail-gw0-f52.google.com [74.125.83.52]) by fiordland.canonical.com (Postfix) with ESMTP id 62720A18A0A for ; Fri, 26 Aug 2011 09:59:26 +0000 (UTC) Received: by gwj15 with SMTP id 15so3731816gwj.11 for ; Fri, 26 Aug 2011 02:59:25 -0700 (PDT) Received: by 10.150.166.7 with SMTP id o7mr2032039ybe.98.1314352765830; Fri, 26 Aug 2011 02:59:25 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.151.27.20 with SMTP id e20cs276928ybj; Fri, 26 Aug 2011 02:59:24 -0700 (PDT) Received: by 10.236.146.65 with SMTP id q41mr5237561yhj.84.1314352764543; Fri, 26 Aug 2011 02:59:24 -0700 (PDT) Received: from mail.codesourcery.com (mail.codesourcery.com [38.113.113.100]) by mx.google.com with ESMTPS id u45si5653536yhu.94.2011.08.26.02.59.23 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 26 Aug 2011 02:59:23 -0700 (PDT) Received-SPF: pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) client-ip=38.113.113.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) smtp.mail=ams@codesourcery.com Received: (qmail 32506 invoked from network); 26 Aug 2011 09:59:21 -0000 Received: from unknown (HELO ?192.168.0.104?) (ams@127.0.0.2) by mail.codesourcery.com with ESMTPA; 26 Aug 2011 09:59:21 -0000 Message-ID: <4E576E76.5040000@codesourcery.com> Date: Fri, 26 Aug 2011 10:59:18 +0100 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:6.0) Gecko/20110812 Thunderbird/6.0 MIME-Version: 1.0 To: "Stubbs, Andrew" CC: Ramana Radhakrishnan , gcc-patches@gcc.gnu.org, patches@linaro.org Subject: Re: [PATCH][ARM] Add support for ADDW and SUBW instructions References: <4DAEFB5C.8020802@codesourcery.com> <4DE751DF.8080906@codesourcery.com> <1A77B5B39081C241A68E6CF16983025F020906BF@EU1-MAIL.mgc.mentorg.com> In-Reply-To: <1A77B5B39081C241A68E6CF16983025F020906BF@EU1-MAIL.mgc.mentorg.com> On 16/06/11 10:13, Stubbs, Andrew wrote: > On 02/06/11 11:36, Ramana Radhakrishnan wrote: >> OK. > > I've not yet committed this patch because my final testing revealed an > unexpected bootstrap failure. I'm still investigating. > > I'll commit or post a replacement soon ... ish. Ok, it wasn't very soon, but I've now committed this patch. In fact the bug was in my thumb2 replicated constants patch, so this one is committed unchanged. Actual patch updated for current baseline attached. Andrew 2011-08-26 Andrew Stubbs gcc/ * config/arm/arm-protos.h (const_ok_for_op): Add prototype. * config/arm/arm.c (const_ok_for_op): Add support for addw/subw. Remove prototype. Remove static function type. * config/arm/arm.md (*arm_addsi3): Add addw/subw support. Add arch attribute. * config/arm/constraints.md (Pj, PJ): New constraints. --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -47,6 +47,7 @@ extern bool arm_vector_mode_supported_p (enum machine_mode); extern bool arm_small_register_classes_for_mode_p (enum machine_mode); extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode); extern int const_ok_for_arm (HOST_WIDE_INT); +extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, HOST_WIDE_INT, rtx, rtx, int); extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -82,7 +82,6 @@ inline static int thumb1_index_register_rtx_p (rtx, int); static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); static int thumb_far_jump_used_p (void); static bool thumb_force_lr_save (void); -static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); static rtx emit_sfm (int, int); static unsigned arm_size_return_regs (void); static bool arm_assemble_integer (rtx, unsigned int, int); @@ -2375,7 +2374,7 @@ const_ok_for_arm (HOST_WIDE_INT i) } /* Return true if I is a valid constant for the operation CODE. */ -static int +int const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) { if (const_ok_for_arm (i)) @@ -2392,6 +2391,13 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); case PLUS: + /* See if we can use addw or subw. */ + if (TARGET_THUMB2 + && ((i & 0xfffff000) == 0 + || ((-i) & 0xfffff000) == 0)) + return 1; + /* else fall through. */ + case COMPARE: case EQ: case NE: --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -708,21 +708,24 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk") - (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk") + (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + addw%?\\t%0, %1, %2 + addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 sub%?\\t%0, %1, #%n2 + subw%?\\t%0, %1, #%n2 + subw%?\\t%0, %1, #%n2 #" "TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT - && !(const_ok_for_arm (INTVAL (operands[2])) - || const_ok_for_arm (-INTVAL (operands[2]))) + && !const_ok_for_op (INTVAL (operands[2]), PLUS) && (reload_completed || !arm_eliminable_register (operands[1]))" [(clobber (const_int 0))] " @@ -731,8 +734,9 @@ operands[1], 0); DONE; " - [(set_attr "length" "4,4,4,4,4,16") - (set_attr "predicable" "yes")] + [(set_attr "length" "4,4,4,4,4,4,4,4,4,16") + (set_attr "predicable" "yes") + (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")] ) (define_insn_and_split "*thumb1_addsi3" --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -31,7 +31,7 @@ ;; The following multi-letter normal constraints have been used: ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz ;; in Thumb-1 state: Pa, Pb, Pc, Pd -;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px, Py +;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us @@ -75,6 +75,18 @@ (and (match_code "const_int") (match_test "(ival & 0xffff0000) == 0"))))) +(define_constraint "Pj" + "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)" + (and (match_code "const_int") + (and (match_test "TARGET_THUMB2") + (match_test "(ival & 0xfffff000) == 0")))) + +(define_constraint "PJ" + "@internal A constant that satisfies the Pj constrant if negated." + (and (match_code "const_int") + (and (match_test "TARGET_THUMB2") + (match_test "((-ival) & 0xfffff000) == 0")))) + (define_register_constraint "k" "STACK_REG" "@internal The stack register.")