From patchwork Fri Mar 30 11:15:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 7532 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4BE6F1991DE for ; Fri, 30 Mar 2012 11:16:09 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id ECF31A1879C for ; Fri, 30 Mar 2012 11:16:08 +0000 (UTC) Received: by iage36 with SMTP id e36so1177621iag.11 for ; Fri, 30 Mar 2012 04:16:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:message-id :date:from:user-agent:mime-version:cc:subject:references:in-reply-to :x-originalarrivaltime:x-gm-message-state:content-type; bh=GAXs8hKzmodzs9xz7DKIAJ3OPAL7VYn8fffj1rIUc+M=; b=ShRlygNYWHrthHg8zw3waH6/Aisf6npvrXVZXolZe9ItAGTYGEC/0M5C7gU1tr3vlQ exK5I87QpckqCr5dzhObNyLBsB9aBglAfIQI5Uu8uN0+TVBbpJzLyaOyj91DGPUElsQ8 xSrTjZMAxWhUWNE1nkAdPQ8ey2yg7aAXLiQxknyAvAyzh2DDNSkoSxdWsA4lzs+vWR39 ZIViJxGbBoErEEJ6RBGpnwDIeNg8Ds5OYqYut2/Fx7VL+j9/IyF2t06TzdX9h7l6VgaW AjdB29gt/983Y1xxsdu2FAUdoCkrPtq1QSK/QEPBMRBpL0fdC+O9mecjvGLuBPDyJExx HSSw== Received: by 10.50.45.234 with SMTP id q10mr1039420igm.54.1333106168427; Fri, 30 Mar 2012 04:16:08 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp17081ibw; Fri, 30 Mar 2012 04:16:07 -0700 (PDT) Received: by 10.180.85.69 with SMTP id f5mr5400378wiz.18.1333106166603; Fri, 30 Mar 2012 04:16:06 -0700 (PDT) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id o6si2170378wiz.33.2012.03.30.04.16.05 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 04:16:06 -0700 (PDT) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1SDZoJ-0006wZ-16 from Andrew_Stubbs@mentor.com ; Fri, 30 Mar 2012 04:16:03 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 30 Mar 2012 04:15:27 -0700 Received: from [172.30.12.11] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Fri, 30 Mar 2012 12:16:01 +0100 Message-ID: <4F7595ED.8070900@codesourcery.com> Date: Fri, 30 Mar 2012 12:15:57 +0100 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120310 Thunderbird/11.0 MIME-Version: 1.0 CC: "gcc-patches@gcc.gnu.org" , "patches@linaro.org" Subject: Re: [PATCH][ARM] NEON DImode immediate constants References: <4F4CFEC6.2090705@codesourcery.com> In-Reply-To: <4F4CFEC6.2090705@codesourcery.com> X-OriginalArrivalTime: 30 Mar 2012 11:15:27.0530 (UTC) FILETIME=[690990A0:01CD0E66] X-Gm-Message-State: ALoCoQnxdFJ0mwVZ3XmN9k6U97JgpA7SVUpyAvj/TlpRte7ZpVB6qaMbqz58zOXJthew+6SuMnMP On 28/02/12 16:20, Andrew Stubbs wrote: > Hi all, > > This patch implements 64-bit immediate constant loads in NEON. > > The current state is that you can load const_vector, but not const_int. > This is clearly not ideal. The result is a constant pool entry when it's > not necessary. > > The patch disables the movdi_vfp patterns for loading DImode values, if > the operand is const_int and NEON is enabled, and extends the neon_mov > pattern to include DImode const_int, as well as the const_vector > operands. I've modified neon_valid_immediate only enough to accept > const_int input - the logic remains untouched. That patch failed to bootstrap successfully, but this updated patch bootstraps and tests with no regressions. OK? Andrew 2012-03-27 Andrew Stubbs gcc/ * config/arm/arm.c (neon_valid_immediate): Allow const_int. (arm_print_operand): Add 'x' format. * config/arm/constraints.md (Dn): Allow const_int. * config/arm/neon.md (neon_mov): Use VDX to allow DImode. Use 'x' format to print constants. * config/arm/predicates.md (imm_for_neon_mov_operand): Allow const_int. * config/arm/vfp.md (movdi_vfp): Disable for const_int when neon is enabled. (movdi_vfp_cortexa8): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 0bded8d..492ddde 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8873,11 +8873,25 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, break; \ } - unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); - unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + unsigned int i, elsize = 0, idx = 0, n_elts; + unsigned int innersize; unsigned char bytes[16]; int immtype = -1, matches; unsigned int invmask = inverse ? 0xff : 0; + bool vector = GET_CODE (op) == CONST_VECTOR; + + if (vector) + { + n_elts = CONST_VECTOR_NUNITS (op); + innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + } + else + { + n_elts = 1; + if (mode == VOIDmode) + mode = DImode; + innersize = GET_MODE_SIZE (mode); + } /* Vectors of float constants. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) @@ -8913,7 +8927,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, /* Splat vector constant out into a byte vector. */ for (i = 0; i < n_elts; i++) { - rtx el = CONST_VECTOR_ELT (op, i); + rtx el = vector ? CONST_VECTOR_ELT (op, i) : op; unsigned HOST_WIDE_INT elpart; unsigned int part, parts; @@ -17230,6 +17244,19 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + /* An integer that we want to print in HEX. */ + case 'x': + switch (GET_CODE (x)) + { + case CONST_INT: + fprintf (stream, "#" HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); + break; + + default: + output_operand_lossage ("Unsupported operand for code '%c'", code); + } + return; + case 'B': if (GET_CODE (x) == CONST_INT) { diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 7d0269a..68979c1 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -255,9 +255,9 @@ (define_constraint "Dn" "@internal - In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov - immediate instruction." - (and (match_code "const_vector") + In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a + Neon vmov immediate instruction." + (and (match_code "const_vector,const_int") (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, GET_MODE (op))"))) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index d7caa37..3c88568 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -152,9 +152,9 @@ (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd")) (define_insn "*neon_mov" - [(set (match_operand:VD 0 "nonimmediate_operand" + [(set (match_operand:VDX 0 "nonimmediate_operand" "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") - (match_operand:VD 1 "general_operand" + (match_operand:VDX 1 "general_operand" " w,w, Dn,Uvi, w, r, r, Usi,r"))] "TARGET_NEON && (register_operand (operands[0], mode) @@ -173,7 +173,7 @@ if (width == 0) return "vmov.f32\t%P0, %1 @ "; else - sprintf (templ, "vmov.i%d\t%%P0, %%1 @ ", width); + sprintf (templ, "vmov.i%d\t%%P0, %%x1 @ ", width); return templ; } diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index b535335..8a8a1f1 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -630,7 +630,7 @@ }) (define_predicate "imm_for_neon_mov_operand" - (match_code "const_vector") + (match_code "const_vector,const_int") { return neon_immediate_valid_for_move (op, mode, NULL, NULL); }) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 6530570..2061414 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -138,7 +138,9 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" + || register_operand (operands[1], DImode)) + && !(TARGET_NEON && CONST_INT_P (operands[1]) + && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" "* switch (which_alternative) { @@ -187,7 +189,9 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" + || register_operand (operands[1], DImode)) + && !(TARGET_NEON && CONST_INT_P (operands[1]) + && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" "* switch (which_alternative) {