From patchwork Fri Jan 4 10:06:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Gretton-Dann X-Patchwork-Id: 13799 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D18C323EDB for ; Fri, 4 Jan 2013 10:06:36 +0000 (UTC) Received: from mail-vb0-f53.google.com (mail-vb0-f53.google.com [209.85.212.53]) by fiordland.canonical.com (Postfix) with ESMTP id 65E0EA183BC for ; Fri, 4 Jan 2013 10:06:36 +0000 (UTC) Received: by mail-vb0-f53.google.com with SMTP id b23so16393907vbz.12 for ; Fri, 04 Jan 2013 02:06:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:message-id:date:from:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :x-gm-message-state; bh=y8HRVla+ZoWgGSwGl3CO4W4Bv1BxDLncB7oUQRkxXXY=; b=bSFVX3GV/WLZza23s3QC/5YFRoDQBtPPPnM1PwZS57NrThgzbbNPad+M+uRY5O/+La 2vRrQjIvJvQe31pzfs5GvK1OowZsDoh9IuncbcC+2E0x3eZeDmQQqEQ34lkJn4+PQTl+ H4aFtnRZ8bvu7byY/hsGGVOoEwXAyAIuKYiAwmrgAw7RhjxSuhFAZPrZzZq3+ysGSsAl Du88KS/VCgQS8TrSTZ1Uhqyr06iLWefjtXL6YTM2K9LGIMrYWb403z0f7PAogHukH6Wu X65NmP+RVJGFPjEeRsbd/36r++LJTm3rocNZNRtQTJa3nFUy+9Sugik1CliMNIekOgkI FtZw== X-Received: by 10.52.18.147 with SMTP id w19mr66873653vdd.94.1357293995822; Fri, 04 Jan 2013 02:06:35 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp129726veb; Fri, 4 Jan 2013 02:06:34 -0800 (PST) X-Received: by 10.204.145.217 with SMTP id e25mr26051767bkv.123.1357293993964; Fri, 04 Jan 2013 02:06:33 -0800 (PST) Received: from mail-bk0-f41.google.com (mail-bk0-f41.google.com [209.85.214.41]) by mx.google.com with ESMTPS id gk3si87557655bkc.11.2013.01.04.02.06.33 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Jan 2013 02:06:33 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.41 is neither permitted nor denied by best guess record for domain of matthew.gretton-dann@linaro.org) client-ip=209.85.214.41; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.41 is neither permitted nor denied by best guess record for domain of matthew.gretton-dann@linaro.org) smtp.mail=matthew.gretton-dann@linaro.org Received: by mail-bk0-f41.google.com with SMTP id jg9so7126890bkc.28 for ; Fri, 04 Jan 2013 02:06:33 -0800 (PST) X-Received: by 10.204.5.133 with SMTP id 5mr25255816bkv.68.1357293992448; Fri, 04 Jan 2013 02:06:32 -0800 (PST) Received: from [172.17.2.134] ([46.208.101.143]) by mx.google.com with ESMTPS id y11sm35944655bkw.8.2013.01.04.02.06.30 (version=SSLv3 cipher=OTHER); Fri, 04 Jan 2013 02:06:31 -0800 (PST) Message-ID: <50E6A9A5.5040706@linaro.org> Date: Fri, 04 Jan 2013 10:06:29 +0000 From: Matthew Gretton-Dann User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: ramrad01@arm.com, Richard Earnshaw , doko@canonical.com, Patch Tracking , Richard Biener Subject: [RFA/ARM/4.7] Fix PR54974: Thumb literal pools don't handle PC rounding References: <2179328.yVVT7qyyS9@e103209-lin> In-Reply-To: X-Gm-Message-State: ALoCoQkl7jmCVxWYKr1k4/In11Ei5cSn3ncbxqtd8IIZIFnZx2wY7ITI+O+tGMtgJFF0znW0AOkq On 29/11/12 14:42, Matthew Gretton-Dann wrote: > On 24 November 2012 00:27, Ramana Radhakrishnan > wrote: >> On Wed, Nov 21, 2012 at 7:59 PM, Matthew Gretton-Dann >> wrote: > [snip] >>> The fix is to decrease the pool_range of all insns by 2 when generating >>> Thumb code. There is no need to change neg_pool_range values as rounding >>> down here will reduce the distance of the literal pool. >> >> A comment about this fact around thumb2_pool_range would be appropriate. >> > [snip] >>> >>> Tested arm-none-linux-gnueabi cross, and with the testcase attached to the >>> PR. No added testcase in the patch as this code is sensitive to other code >>> generation and so it is not easy to generate a testcase which will reliably >>> test this condition. >>> >>> OK for trunk, 4.7, and 4.6? >> >> >> Ok for trunk today - please wait a few days before backporting into >> 4.6 and 4.7 to see what the fallout is like . Watch out for any >> fallout with the auto-testers. No fallout has been seen with the auto-testers. > The attached is what was actually committed as revision 193930 > (original patch + requested comment). The attached patch is a backport of the trunk patch to 4.7. Cross tested arm-none-linux-gnueabi with QEMU OK for 4.7? Thanks, Matt 2013-01-04 Matthew Gretton-Dann Backport from mainline. 2012-11-29 Matthew Gretton-Dann PR target/54974 * config/arm/arm.md (thumb2_pool_range, pool_range): Add comment on Thumb pool ranges. (thumb1_extendhisi2): Reduce Thumb pool range. (arm_movdi): Likewise. (thumb1_movdi_insn): Likewise. (thumb1_movsi_insn): Likewise. (pic_load_addr_unified): Likewise. (pic_load_addr_32bit): Likewise. (pic_load_addr_thumb1): Likewise. (thumb1_movhf): Likewise. (arm_movsf_soft_insn): Likewise. (thumb1_movsf_soft_insn): Likewise. (movdf_soft_insn): Likewise. (thumb1_movdf_soft_insn): Likewise. * config/arm/neon.md (*neon_mov): Likewise. (*neon_mov): Likwise. * config/arm/thumb2.md: (*thumb2_movsi_insn): Likewise. (*thumb2_movhi_insn): Likewise. (*thumb2_extendqisi_v6): Likewise. (*thumb2_zero_extendqisi_v6): Likewise. (*thumb2_zero_extendqisi2_v6): Likewise. * config/arm/vfp.md: (*thumb2_movsi_vfp): Likewise. (*movdi_vfp): Likewise. (*movdi_vfp_cortexa8): Likewise. (*thumb2_movsf_vfp): Likewise. (*thumb2_movdf_vfp): Likewise. Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 194852) +++ gcc/config/arm/arm.md (working copy) @@ -256,6 +256,9 @@ (define_attr "insn_enabled" "no,yes" ; POOL_RANGE is how far away from a constant pool entry that this insn ; can be placed. If the distance is zero, then this insn will never ; reference the pool. +; Note that for Thumb constant pools the PC value is rounded down to the +; nearest multiple of four. Therefore, THUMB2_POOL_RANGE (and POOL_RANGE for +; Thumb insns) should be set to - 2. ; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry ; before its address. It is set to - (8 + ). (define_attr "arm_pool_range" "" (const_int 0)) @@ -4833,7 +4836,7 @@ (define_insn "thumb1_extendhisi2" (const_int 2) (const_int 4)) (const_int 4)]) (set_attr "type" "alu_shift,load_byte") - (set_attr "pool_range" "*,1020")] + (set_attr "pool_range" "*,1018")] ) ;; This pattern will only be used when ldsh is not available @@ -5239,7 +5242,7 @@ (define_insn "*arm_movdi" (set_attr "type" "*,*,*,load2,store2") (set_attr "arm_pool_range" "*,*,*,1020,*") (set_attr "arm_neg_pool_range" "*,*,*,1004,*") - (set_attr "thumb2_pool_range" "*,*,*,4096,*") + (set_attr "thumb2_pool_range" "*,*,*,4094,*") (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")] ) @@ -5379,7 +5382,7 @@ (define_insn "*thumb1_movdi_insn" [(set_attr "length" "4,4,6,2,2,6,4,4") (set_attr "type" "*,*,*,load2,store2,load2,store2,*") (set_attr "insn" "*,mov,*,*,*,*,*,mov") - (set_attr "pool_range" "*,*,*,*,*,1020,*,*")] + (set_attr "pool_range" "*,*,*,*,*,1018,*,*")] ) (define_expand "movsi" @@ -5539,7 +5542,7 @@ (define_insn "*thumb1_movsi_insn" mov\\t%0, %1" [(set_attr "length" "2,2,4,4,2,2,2,2,2") (set_attr "type" "*,*,*,*,load1,store1,load1,store1,*") - (set_attr "pool_range" "*,*,*,*,*,*,1020,*,*") + (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*") (set_attr "conds" "set,clob,*,*,nocond,nocond,nocond,nocond,nocond")]) (define_split @@ -5632,7 +5635,7 @@ (define_insn_and_split "pic_load_addr_un (match_dup 2)] UNSPEC_PIC_BASE))] "operands[3] = TARGET_THUMB ? GEN_INT (4) : GEN_INT (8);" [(set_attr "type" "load1,load1,load1") - (set_attr "pool_range" "4096,4096,1024") + (set_attr "pool_range" "4096,4094,1022") (set_attr "neg_pool_range" "4084,0,0") (set_attr "arch" "a,t2,t1") (set_attr "length" "8,6,4")] @@ -5648,7 +5651,10 @@ (define_insn "pic_load_addr_32bit" "TARGET_32BIT && flag_pic" "ldr%?\\t%0, %1" [(set_attr "type" "load1") - (set_attr "pool_range" "4096") + (set (attr "pool_range") + (if_then_else (eq_attr "is_thumb" "no") + (const_int 4096) + (const_int 4094))) (set (attr "neg_pool_range") (if_then_else (eq_attr "is_thumb" "no") (const_int 4084) @@ -5661,7 +5667,7 @@ (define_insn "pic_load_addr_thumb1" "TARGET_THUMB1 && flag_pic" "ldr\\t%0, %1" [(set_attr "type" "load1") - (set (attr "pool_range") (const_int 1024))] + (set (attr "pool_range") (const_int 1018))] ) (define_insn "pic_add_dot_plus_four" @@ -6456,7 +6462,7 @@ (define_insn "*thumb1_movhf" [(set_attr "length" "2") (set_attr "type" "*,load1,store1,*,*") (set_attr "insn" "mov,*,*,mov,mov") - (set_attr "pool_range" "*,1020,*,*,*") + (set_attr "pool_range" "*,1018,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond")]) (define_expand "movsf" @@ -6511,7 +6517,8 @@ (define_insn "*arm_movsf_soft_insn" [(set_attr "predicable" "yes") (set_attr "type" "*,load1,store1") (set_attr "insn" "mov,*,*") - (set_attr "pool_range" "*,4096,*") + (set_attr "arm_pool_range" "*,4096,*") + (set_attr "thumb2_pool_range" "*,4094,*") (set_attr "arm_neg_pool_range" "*,4084,*") (set_attr "thumb2_neg_pool_range" "*,0,*")] ) @@ -6533,7 +6540,7 @@ (define_insn "*thumb1_movsf_insn" mov\\t%0, %1" [(set_attr "length" "2") (set_attr "type" "*,load1,store1,load1,store1,*,*") - (set_attr "pool_range" "*,*,*,1020,*,*,*") + (set_attr "pool_range" "*,*,*,1018,*,*,*") (set_attr "insn" "*,*,*,*,*,mov,mov") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")] ) @@ -6622,7 +6629,8 @@ (define_insn "*movdf_soft_insn" " [(set_attr "length" "8,12,16,8,8") (set_attr "type" "*,*,*,load2,store2") - (set_attr "pool_range" "*,*,*,1020,*") + (set_attr "arm_pool_range" "*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*") (set_attr "arm_neg_pool_range" "*,*,*,1004,*") (set_attr "thumb2_neg_pool_range" "*,*,*,0,*")] ) @@ -6665,7 +6673,7 @@ (define_insn "*thumb_movdf_insn" [(set_attr "length" "4,2,2,6,4,4") (set_attr "type" "*,load2,store2,load2,store2,*") (set_attr "insn" "*,*,*,*,*,mov") - (set_attr "pool_range" "*,*,*,1020,*,*")] + (set_attr "pool_range" "*,*,*,1018,*,*")] ) (define_expand "movxf" Index: gcc/config/arm/neon.md =================================================================== --- gcc/config/arm/neon.md (revision 194852) +++ gcc/config/arm/neon.md (working copy) @@ -201,7 +201,8 @@ (define_insn "*neon_mov" (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu,load2,store2") (set_attr "insn" "*,*,*,*,*,*,mov,*,*") (set_attr "length" "4,4,4,4,4,4,8,8,8") - (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,1004,*,*,*,1004,*")]) (define_insn "*neon_mov" @@ -246,7 +247,8 @@ (define_insn "*neon_mov" (set_attr "type" "*,*,*,*,*,*,alu,load4,store4") (set_attr "insn" "*,*,*,*,*,*,mov,*,*") (set_attr "length" "4,8,4,8,8,8,16,8,16") - (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,996,*,*,*,996,*")]) (define_expand "movti" Index: gcc/config/arm/vfp.md =================================================================== --- gcc/config/arm/vfp.md (revision 194852) +++ gcc/config/arm/vfp.md (working copy) @@ -126,7 +126,7 @@ (define_insn "*thumb2_movsi_vfp" [(set_attr "predicable" "yes") (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*") - (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") + (set_attr "pool_range" "*,*,*,*,1018,4094,*,*,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] ) @@ -177,7 +177,8 @@ (define_insn "*movdi_vfp" (const_int 8) (const_int 4))] (const_int 4))) - (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") + (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] ) @@ -222,7 +223,8 @@ (define_insn "*movdi_vfp_cortexa8" * 4")] (const_int 4))) (set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") + (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") + (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") (set (attr "ce_count") (symbol_ref "get_attr_length (insn) / 4")) @@ -409,7 +411,7 @@ (define_insn "*thumb2_movsf_vfp" (set_attr "type" "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") (set_attr "insn" "*,*,*,*,*,*,*,*,mov") - (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") + (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] ) @@ -501,7 +503,7 @@ (define_insn "*thumb2_movdf_vfp" (const_int 8) (const_int 4))] (const_int 4))) - (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") + (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] ) Index: gcc/config/arm/thumb2.md =================================================================== --- gcc/config/arm/thumb2.md (revision 194852) +++ gcc/config/arm/thumb2.md (working copy) @@ -182,7 +182,7 @@ (define_insn "*thumb2_movsi_insn" str%?\\t%1, %0" [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") + (set_attr "pool_range" "*,*,*,*,1018,4094,*,*") (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] ) @@ -217,7 +217,7 @@ (define_insn "*thumb2_movhi_insn" ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "type" "*,*,store1,load1") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,4096") + (set_attr "pool_range" "*,*,*,4094") (set_attr "neg_pool_range" "*,*,*,250")] ) @@ -570,7 +570,7 @@ (define_insn "*thumb2_extendqisi_v6" ldr%(sb%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,4096") + (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -583,7 +583,7 @@ (define_insn "*thumb2_zero_extendhisi2_v ldr%(h%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,4096") + (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -596,7 +596,7 @@ (define_insn "thumb2_zero_extendqisi2_v6 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,4096") + (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] )