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[58.6.183.210]) by mx.google.com with ESMTPSA id ax2sm5167244pac.21.2015.04.15.16.00.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2015 16:00:52 -0700 (PDT) Message-ID: <552EED9F.3060901@linaro.org> Date: Thu, 16 Apr 2015 09:00:47 +1000 From: Kugan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Jakub Jelinek CC: Richard Earnshaw , "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , James Greenhalgh , Maxim Kuvyrkov Subject: Re: [AArch64][PR65139] use clobber with match_scratch for aarch64_lshr_sisd_or_int_3 References: <552D897C.2040207@linaro.org> <552E571C.3000306@foss.arm.com> <20150415123202.GW1725@tucnak.redhat.com> <552EE5CC.9040703@linaro.org> <20150415223248.GZ1725@tucnak.redhat.com> In-Reply-To: <20150415223248.GZ1725@tucnak.redhat.com> X-IsSubscribed: yes X-Original-Sender: kugan.vivekanandarajah@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 16/04/15 08:32, Jakub Jelinek wrote: > On Thu, Apr 16, 2015 at 08:27:24AM +1000, Kugan wrote: >> + if ( == LSHIFTRT) >> + { >> + emit_insn (gen_aarch64_lshr_sisd_or_int_3 (operands[0], operands[1], operands[2])); > > That is way too long line, please wrap it. > >> + DONE; >> + } >> } >> ) >> >> @@ -3361,11 +3367,12 @@ >> ) >> >> ;; Logical right shift using SISD or Integer instruction >> -(define_insn "*aarch64_lshr_sisd_or_int_3" >> - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r") >> +(define_insn "aarch64_lshr_sisd_or_int_3" >> + [(set (match_operand:GPI 0 "register_operand" "=w,w,r") >> (lshiftrt:GPI >> (match_operand:GPI 1 "register_operand" "w,w,r") >> - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs")))] >> + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs"))) > > Though, this one too... > Fixed in the attached patch. Thanks, Kugan diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 534a862..72a9f05 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3277,6 +3277,14 @@ DONE; } } + + if ( == LSHIFTRT) + { + emit_insn (gen_aarch64_lshr_sisd_or_int_3 (operands[0], + operands[1], + operands[2])); + DONE; + } } ) @@ -3361,11 +3369,13 @@ ) ;; Logical right shift using SISD or Integer instruction -(define_insn "*aarch64_lshr_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r") +(define_insn "aarch64_lshr_sisd_or_int_3" + [(set (match_operand:GPI 0 "register_operand" "=w,w,r") (lshiftrt:GPI (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs")))] + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" + "Us,w,rUs"))) + (clobber (match_scratch:QI 3 "=X,w,X"))] "" "@ ushr\t%0, %1, %2 @@ -3379,30 +3389,28 @@ [(set (match_operand:DI 0 "aarch64_simd_register") (lshiftrt:DI (match_operand:DI 1 "aarch64_simd_register") - (match_operand:QI 2 "aarch64_simd_register")))] + (match_operand:QI 2 "aarch64_simd_register"))) + (clobber (match_scratch:QI 3))] "TARGET_SIMD && reload_completed" [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_SISD_USHL))] - { - operands[3] = gen_lowpart (QImode, operands[0]); - } + "" ) (define_split [(set (match_operand:SI 0 "aarch64_simd_register") (lshiftrt:SI (match_operand:SI 1 "aarch64_simd_register") - (match_operand:QI 2 "aarch64_simd_register")))] + (match_operand:QI 2 "aarch64_simd_register"))) + (clobber (match_scratch:QI 3))] "TARGET_SIMD && reload_completed" [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) (unspec:SI [(match_dup 1) (match_dup 3)] UNSPEC_USHL_2S))] - { - operands[3] = gen_lowpart (QImode, operands[0]); - } + "" ) ;; Arithmetic right shift using SISD or Integer instruction