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[58.6.183.210]) by mx.google.com with ESMTPSA id fk4sm12081941pbb.80.2015.04.24.16.30.22 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Apr 2015 16:30:25 -0700 (PDT) Message-ID: <553AD20A.9020108@linaro.org> Date: Sat, 25 Apr 2015 09:30:18 +1000 From: Kugan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: James Greenhalgh CC: Kyrylo Tkachov , "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Richard Earnshaw , Jim Wilson Subject: [ARM] Fix RTX cost for vector SET References: <5506D77B.5060909@linaro.org> <55070972.3000800@arm.com> <5507813E.3060106@linaro.org> <5513B390.2030201@linaro.org> <552D8FF7.5000105@linaro.org> <20150415092509.GA20852@arm.com> <552E4150.3020403@linaro.org> <20150415111854.GB22143@arm.com> <552E4C90.4070208@linaro.org> <5530EC32.4030806@linaro.org> <20150420202225.GA7414@arm.com> <553AD118.3010705@linaro.org> In-Reply-To: <553AD118.3010705@linaro.org> X-IsSubscribed: yes X-Original-Sender: kugan.vivekanandarajah@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22e as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 > > Thanks for the review. I have updated the patch based on the comments > with some other minor changes. Bootstrapped and regression tested on > aarch64-none-linux-gnu with no-new regressions. Is this OK for trunk? > > > Thanks, > Kugan > > > gcc/ChangeLog: > > 2015-04-24 Kugan Vivekanandarajah > Jim Wilson > > * config/arm/aarch-common-protos.h (struct mem_cost_table): Added > new fields loadv and storev. > * config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs): > Initialize loadv and storev. > * config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise. > (cortexa53_extra_costs): Likewise. > (cortexa57_extra_costs): Likewise. > (xgene1_extra_costs): Likewise. > * config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector > rtx_costs. > Due to the struct mem_cost_table update for aarch64, arm cost tables also need to be updated. Please find the patch that does this. Regression tested on arm-none-linux-gnu with no-new regressions. Is this OK for trunk? Thanks, Kugan gcc/ChangeLog: 2015-04-25 Kugan Vivekanandarajah * config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and storev. (cortexa8_extra_costs): Likewise. (cortexa5_extra_costs): Likewise. (cortexa7_extra_costs): Likewise. (cortexa12_extra_costs): Likewise. (cortexa15_extra_costs): Likewise. (v7m_extra_costs): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6826c78..d43239a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1027,7 +1027,9 @@ const struct cpu_cost_table cortexa9_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* stored. */ - COSTS_N_INSNS (1) /* store_unaligned. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1128,7 +1130,9 @@ const struct cpu_cost_table cortexa8_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* stored. */ - COSTS_N_INSNS (1) /* store_unaligned. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1230,7 +1234,9 @@ const struct cpu_cost_table cortexa5_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* stored. */ - COSTS_N_INSNS (1) /* store_unaligned. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1333,7 +1339,9 @@ const struct cpu_cost_table cortexa7_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* stored. */ - COSTS_N_INSNS (1) /* store_unaligned. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1434,7 +1442,9 @@ const struct cpu_cost_table cortexa12_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* stored. */ - 0 /* store_unaligned. */ + 0, /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1535,7 +1545,9 @@ const struct cpu_cost_table cortexa15_extra_costs = 2, /* stm_regs_per_insn_subsequent. */ 0, /* storef. */ 0, /* stored. */ - 0 /* store_unaligned. */ + 0, /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */ @@ -1636,7 +1648,9 @@ const struct cpu_cost_table v7m_extra_costs = 1, /* stm_regs_per_insn_subsequent. */ COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (3), /* stored. */ - COSTS_N_INSNS (1) /* store_unaligned. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ }, { /* FP SFmode */