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[209.132.180.131]) by mx.google.com with ESMTPS id y189si30797680pfg.169.2016.11.16.00.46.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Nov 2016 00:46:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-441584-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-441584-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-441584-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=E/KQDXW7SNm8krYly8EgIdiOIivrpHTYvEEkmOfaHAt Swqb+lRtVuG1OyFEiBx55itS6sZqglVhluBo6B5HIgrzLpgAiojo97z6Mj7szw9Z FC9YgXVOLHcylq3H0fWnKEB2fH3oKd5mXingpRJlesxVqaxGtKRBoKtWHhczYXjk = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=vGl3LzAfnArqUQYXD7324aG9Ig8=; b=msb7yOy6L0vBEnYTM gAUVVZVHu/wLosFrOZh7OmnE4/3KDaBQ1JA0vVvygsdYURsGvqV20BOCFq5xkQWK EkcLn+/U09rX3LO1nzuCuvp782nywGZ7PK9udc28wBe6qk1TziVD7cq7Oo4r/0So ULBAqpqbKTTWzvUFOeM6Ryh/gg= Received: (qmail 21918 invoked by alias); 16 Nov 2016 08:45:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21905 invoked by uid 89); 16 Nov 2016 08:45:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Cc, translates, 2016-11-16, interest X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Nov 2016 08:45:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DEA6913D5; Wed, 16 Nov 2016 00:45:37 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4D6263F24D; Wed, 16 Nov 2016 00:45:37 -0800 (PST) Message-ID: <582C1CAF.4050402@foss.arm.com> Date: Wed, 16 Nov 2016 08:45:35 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] PR target/78364: Add proper restrictions to zero and sign_extract patterns operands Hi all, This patch fixes the arm build failure due to out of range ubfx operands. Combine now more aggressively generates zero_extracts and it's up to the backend to reject invalid bit offsets and widths. And arm seems to suffer from the same problems as aarch64 and s390 did in PR 77822. My ARMv7-A and ARMv7-R Architecture Reference Manual version C.c in section A8.8.246 says that the bit offset () should be in the range 0 to 31 whereas the width should be in the range 1 to 32 - . Same for SBFX. This patch directly translates those restrictions into range checks on operands 2 and 3 of the relevant patterns. With this patch the arm build succeeds. Bootstrapped and tested on arm-none-linux-gnueabihf. Committing to trunk in the interest of fixing the build. Thanks, Kyrill 2016-11-16 Kyrylo Tkachov PR target/78364 * config/arm/arm.md (*extv_reg): Restrict operands 2 and 3 to the proper ranges for an SBFX instruction. (extzv_t2): Likewise for UBFX. commit b9ea5a6274834cbc469988040a807093156b52cf Author: Kyrylo Tkachov Date: Tue Nov 15 15:53:21 2016 +0000 [ARM] PR target/78364: Add proper restrictions to zero and sign_extract patterns operands diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ac3ef15..87b5ea6 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4561,9 +4561,11 @@ (define_insn "unaligned_storehi" (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_M_operand" "M") - (match_operand:SI 3 "const_int_M_operand" "M")))] - "arm_arch_thumb2" + (match_operand:SI 2 "const_int_operand" "n") + (match_operand:SI 3 "const_int_operand" "n")))] + "arm_arch_thumb2 + && IN_RANGE (INTVAL (operands[3]), 0, 31) + && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") @@ -4574,9 +4576,11 @@ (define_insn "*extv_reg" (define_insn "extzv_t2" [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_M_operand" "M") - (match_operand:SI 3 "const_int_M_operand" "M")))] - "arm_arch_thumb2" + (match_operand:SI 2 "const_int_operand" "n") + (match_operand:SI 3 "const_int_operand" "n")))] + "arm_arch_thumb2 + && IN_RANGE (INTVAL (operands[3]), 0, 31) + && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes")