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[209.132.180.131]) by mx.google.com with ESMTPS id 1si28127345pll.154.2016.12.08.01.35.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Dec 2016 01:35:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443770-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443770-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443770-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=BKljIdIbOboXQzsur2BpOD+GNdm6a/8nqZx8VhgoodV UDT9/xCVe9LNaTTmEgvHDhTk47zPZEXxqZ80qWJrMx5OHcejBvb7dguXfB3PdHFW kIJr7jOTIO+SWAUNyjmmbuD4Hj7oIh9Zq8JYmvmWO7sFq3IncJk4PTWNUPWB+zTo = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=vfJbTpTgKIluH5WyZuXi4fO/4X4=; b=H/Axk+KW3Wm/Sh9ZG vIsMPLZiO47SQMnOE50UmInLcJdoYLIbE+pvZJ+aUVhgqkW6QhXL2Ryv81k+dgta ryxVlA3BzJg4aMafz1IGogSkL8lBKchsFS1hpEv09+ybBmKDCzDcMfMuQeeRJ0Hk pjBUNH4Eea8oCrxs9wqFTfgfOM= Received: (qmail 95005 invoked by alias); 8 Dec 2016 09:35:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94964 invoked by uid 89); 8 Dec 2016 09:35:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=gpi, risk X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Dec 2016 09:35:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1EE85C14; Thu, 8 Dec 2016 01:35:11 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B5723F477; Thu, 8 Dec 2016 01:35:10 -0800 (PST) Message-ID: <5849294C.6060109@foss.arm.com> Date: Thu, 08 Dec 2016 09:35:08 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Split X-reg UBFX into W-reg LSR when possible Hi all, In this patch we split X-register UBFX instructions that extract up to the edge of a W-register into a W-register LSR instruction. So for the example in the testcase instead of: UBFX X0, X0, 24, 8 we'd generate: LSR w0, w0, 24 An LSR is a simpler instruction and there's a higher chance that it can be combined with other instructions. To do this the patch separates the sign_extract case from the zero_extract case in the * ANY_EXTRACT pattern and further splits the SImode/DImode patterns from the resulting zrero_extract pattern. The DImode zero_extract pattern then becomes a define_insn_and_split that splits into a zero_extend of an lshiftrt when the bitposition and width of the zero_extract add up to 32. Bootstrapped and tested on aarch64-none-linux-gnu. Since we're in stage 3 perhaps this is not for GCC 6, but it is fairly low risk. I'm happy for it to wait for the next release if necessary. Thanks, Kyrill 2016-12-08 Kyrylo Tkachov * config/aarch64/aarch64.md (*): Split into... (*extv): ...This... (*extzvsi): ...This... (*extzvdi:): ... And this. Add splitting to lshiftrt when possible. 2016-12-08 Kyrylo Tkachov * gcc.target/aarch64/ubfx_lsr_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6b4d0ba633af2a549ded2f18962d9ed300f56e12..a6f659c26bb5156d652b6c1f09123e682e9ff648 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4327,16 +4327,51 @@ (define_expand "" ) -(define_insn "*" +(define_insn "*extv" [(set (match_operand:GPI 0 "register_operand" "=r") - (ANY_EXTRACT:GPI (match_operand:GPI 1 "register_operand" "r") + (sign_extract:GPI (match_operand:GPI 1 "register_operand" "r") (match_operand 2 "aarch64_simd_shift_imm_offset_" "n") (match_operand 3 "aarch64_simd_shift_imm_" "n")))] "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1, GET_MODE_BITSIZE (mode) - 1)" - "bfx\\t%0, %1, %3, %2" + "sbfx\\t%0, %1, %3, %2" + [(set_attr "type" "bfx")] +) + +(define_insn "*extzvsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 + "aarch64_simd_shift_imm_offset_si" "n") + (match_operand 3 + "aarch64_simd_shift_imm_si" "n")))] + "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), + 1, GET_MODE_BITSIZE (SImode) - 1)" + "ubfx\\t%w0, %w1, %3, %2" + [(set_attr "type" "bfx")] +) + +(define_insn_and_split "*extzvdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extract:DI (match_operand:DI 1 "register_operand" "r") + (match_operand 2 + "aarch64_simd_shift_imm_offset_di" "n") + (match_operand 3 + "aarch64_simd_shift_imm_di" "n")))] + "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), + 1, GET_MODE_BITSIZE (DImode) - 1)" + "ubfx\\t%x0, %x1, %3, %2" + ;; When the bitposition and width add up to 32 we can use a W-reg LSR + ;; instruction taking advantage of the implicit zero-extension of the X-reg. + "&& (INTVAL (operands[2]) + INTVAL (operands[3])) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } [(set_attr "type" "bfx")] ) diff --git a/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c b/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c new file mode 100644 index 0000000000000000000000000000000000000000..bc083862976a88190dbef97a247be8a10b277a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFX can be simplified into a W-reg LSR. */ + +int +f (unsigned long long x) +{ + x = (x >> 24) & 255; + return x + 1; +} + +/* { dg-final { scan-assembler "lsr\tw" } } */ +/* { dg-final { scan-assembler-not "ubfx\tx" } } */