From patchwork Thu Dec 15 16:05:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88176 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp879619qgi; Thu, 15 Dec 2016 08:06:37 -0800 (PST) X-Received: by 10.84.209.136 with SMTP id y8mr4055202plh.114.1481817997547; Thu, 15 Dec 2016 08:06:37 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id e85si3089488pfj.218.2016.12.15.08.06.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:06:37 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444518-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444518-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444518-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=SFnvyV08R6zEfCWNUZh5qPYCrU1M7 KUDctbsAYCTgUto36NGz8ZVb/wikgbg9DEmt1bsXdmSSVHk+fNNAKHe7oXfDTq3u ZqJDK1hBtviA7JywU/BgN44cLwIcnNmPkrHjbYo87ZGr2VDMTLOklnUZLy4wfHPd L/KzdOaDvjgEfs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=SXCn0FfUVH1E0EFuLDttX6rCqIY=; b=Eco FXxy+zGIn1Yffhwv5mAdjbgwv6vkZ6mYlWfVCGmMjI+G0KHJyOt50DTDjotqsQMO rbDHBrx48z5r2U0remhXtRqPPYh/LxNBSWC59nhMD83Di9b5Kug/uvlE9VLQeZa1 5s46+pBKJbjb3M5fKfbRhL/GKBz74UIi7OPai5nA= Received: (qmail 31059 invoked by alias); 15 Dec 2016 16:05:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30986 invoked by uid 89); 15 Dec 2016 16:05:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:05:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C46A1516; Thu, 15 Dec 2016 08:05:45 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4EC333F445 for ; Thu, 15 Dec 2016 08:05:45 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 04/21] [arm] Use arm_active_target for architecture and tune operations. To: gcc-patches@gcc.gnu.org References: Message-ID: <76ddc758-5126-0e74-590d-fdb09c4263ca@arm.com> Date: Thu, 15 Dec 2016 16:05:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: We now start to make more use of the new data structure. This allows us to eliminate two of the existing static variables, arm_selected_arch and arm_selected tune. * arm.c (arm_selected_tune): Delete static variable. (arm_selected_arch): Likewise. (arm_configure_build_target): Declare local versions of arm_selected target and arm_selected_arch. Initialize more fields in target data structure. (arm_option_override): Use arm_active_target instead of arm_selected_tune and arm_selected_arch. (asm_file_start): Use arm_active_target. --- gcc/config/arm/arm.c | 58 +++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 17 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index deab528..a4d370c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2319,9 +2319,7 @@ static const struct processors all_architectures[] = /* These are populated as commandline arguments are processed, or NULL if not specified. */ -static const struct processors *arm_selected_arch; static const struct processors *arm_selected_cpu; -static const struct processors *arm_selected_tune; /* The name of the preprocessor macro to define for this architecture. PROFILE is replaced by the architecture name (eg. 8A) in arm_option_override () and @@ -3068,9 +3066,10 @@ arm_configure_build_target (struct arm_build_target *target, struct gcc_options *opts_set, bool warn_compatible) { - arm_selected_arch = NULL; + const struct processors *arm_selected_tune = NULL; + const struct processors *arm_selected_arch = NULL; + arm_selected_cpu = NULL; - arm_selected_tune = NULL; bitmap_clear (target->isa); target->core_name = NULL; @@ -3119,17 +3118,24 @@ arm_configure_build_target (struct arm_build_target *target, Prefer the CPU setting. */ arm_selected_arch = NULL; } + + target->core_name = arm_selected_cpu->name; } else { /* Pick a CPU based on the architecture. */ arm_selected_cpu = arm_selected_arch; target->arch_name = arm_selected_arch->name; + /* Note: target->core_name is left unset in this path. */ } } - + else if (arm_selected_cpu) + { + target->core_name = arm_selected_cpu->name; + arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits); + } /* If the user did not specify a processor, choose one for them. */ - if (!arm_selected_cpu) + else { const struct processors * sel; auto_sbitmap sought_isa (isa_num_bits); @@ -3229,16 +3235,27 @@ arm_configure_build_target (struct arm_build_target *target, } arm_selected_cpu = sel; } + + /* Now we know the CPU, we can finally initialize the target + structure. */ + target->core_name = arm_selected_cpu->name; + arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits); } gcc_assert (arm_selected_cpu); + /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!arm_selected_tune) arm_selected_tune = &all_cores[arm_selected_cpu->core]; + /* Finish initializing the target structure. */ target->arch_pp_name = arm_selected_cpu->arch; + target->base_arch = arm_selected_cpu->base_arch; + target->arch_core = arm_selected_cpu->core; + target->tune_flags = arm_selected_tune->tune_flags; target->tune = arm_selected_tune->tune; + target->tune_core = arm_selected_tune->core; } /* Fix up any incompatible options that the user has specified. */ @@ -3263,9 +3280,9 @@ arm_option_override (void) insn_flags = arm_selected_cpu->flags; arm_base_arch = arm_selected_cpu->base_arch; - arm_tune = arm_selected_tune->core; - tune_flags = arm_selected_tune->tune_flags; - current_tune = arm_selected_tune->tune; + arm_tune = arm_active_target.tune_core; + tune_flags = arm_active_target.tune_flags; + current_tune = arm_active_target.tune; /* TBD: Dwarf info for apcs frame is not handled yet. */ if (TARGET_APCS_FRAME) @@ -25957,10 +25974,16 @@ arm_file_start (void) if (TARGET_BPABI) { - if (arm_selected_arch) + /* We don't have a specified CPU. Use the architecture to + generate the tags. + + Note: it might be better to do this unconditionally, then the + assembler would not need to know about all new CPU names as + they are added. */ + if (!arm_active_target.core_name) { /* armv7ve doesn't support any extensions. */ - if (strcmp (arm_selected_arch->name, "armv7ve") == 0) + if (strcmp (arm_active_target.arch_name, "armv7ve") == 0) { /* Keep backward compatability for assemblers which don't support armv7ve. */ @@ -25972,20 +25995,21 @@ arm_file_start (void) } else { - const char* pos = strchr (arm_selected_arch->name, '+'); + const char* pos = strchr (arm_active_target.arch_name, '+'); if (pos) { char buf[32]; - gcc_assert (strlen (arm_selected_arch->name) + gcc_assert (strlen (arm_active_target.arch_name) <= sizeof (buf) / sizeof (*pos)); - strncpy (buf, arm_selected_arch->name, - (pos - arm_selected_arch->name) * sizeof (*pos)); - buf[pos - arm_selected_arch->name] = '\0'; + strncpy (buf, arm_active_target.arch_name, + (pos - arm_active_target.arch_name) * sizeof (*pos)); + buf[pos - arm_active_target.arch_name] = '\0'; asm_fprintf (asm_out_file, "\t.arch %s\n", buf); asm_fprintf (asm_out_file, "\t.arch_extension %s\n", pos + 1); } else - asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); + asm_fprintf (asm_out_file, "\t.arch %s\n", + arm_active_target.arch_name); } } else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)