diff --git a/contrib/gcc_update b/contrib/gcc_update
index 2df9da4..ab5b33d 100755
--- a/contrib/gcc_update
+++ b/contrib/gcc_update
@@ -80,8 +80,11 @@ gcc/cstamp-h.in: gcc/configure.ac
 gcc/config.in: gcc/cstamp-h.in
 gcc/fixinc/fixincl.x: gcc/fixinc/fixincl.tpl gcc/fixinc/inclhack.def
 gcc/config/aarch64/aarch64-tune.md: gcc/config/aarch64/aarch64-cores.def gcc/config/aarch64/gentune.sh
-gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cores.def gcc/config/arm/gentune.sh
-gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-arches.def gcc/config/arm/arm-cores.def gcc/config/arm/arm-fpus.def gcc/config/arm/genopt.sh
+gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
+gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
+gcc/config/arm/arm-cpu.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
+gcc/config/arm/arm-cpu-data.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
+gcc/config/arm/arm-cpu-cdata.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
 gcc/config/avr/avr-tables.opt: gcc/config/avr/avr-mcus.def gcc/config/avr/genopt.sh
 gcc/config/avr/t-multilib: gcc/config/avr/avr-mcus.def gcc/config/avr/genmultilib.awk
 gcc/config/c6x/c6x-tables.opt: gcc/config/c6x/c6x-isas.def gcc/config/c6x/genopt.sh
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index 4103c67..7ecc68d 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -104,19 +104,7 @@ struct arm_arch_core_flag
   const enum isa_feature isa_bits[isa_num_bits];
 };
 
-static const struct arm_arch_core_flag arm_arch_core_flags[] =
-{
-#undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)	\
-  {NAME, {ISA isa_nobit}},
-#include "config/arm/arm-cores.def"
-#undef ARM_CORE
-#undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)	\
-  {NAME, {ISA isa_nobit}},
-#include "config/arm/arm-arches.def"
-#undef ARM_ARCH
-};
+#include "config/arm/arm-cpu-cdata.h"
 
 /* Scan over a raw feature array BITS checking for BIT being present.
    This is slower than the normal bitmask checks, but we would spend longer
diff --git a/gcc/config.gcc b/gcc/config.gcc
index bb25d54..69fddda 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3660,41 +3660,24 @@ case "${target}" in
 
 	arm*-*-*)
 		supported_defaults="arch cpu float tune fpu abi mode tls"
-		for which in cpu tune; do
-			# See if it matches any of the entries in arm-cores.def
+		for which in cpu tune arch; do
+			# See if it matches a supported value
 			eval "val=\$with_$which"
-			if [ x"$val" = x ] \
-			    || grep "^ARM_CORE(\"$val\"," \
-				    ${srcdir}/config/arm/arm-cores.def \
-				    > /dev/null; then
-			  # Ok
-			  new_val=`grep "^ARM_CORE(\"$val\"," \
-				${srcdir}/config/arm/arm-cores.def | \
-				sed -e 's/^[^,]*,[ 	]*//' | \
-				sed -e 's/,.*$//'`
-			  if [ x"$val" != x ] ; then
-				eval "target_${which}_cname=$new_val"
-				echo "For $val real value is $new_val"
+			if [ x"$val" != x ]; then
+			  cpu=`awk -f ${srcdir}/config/arm/parsecpu.awk \
+				-v cmd="chk$which $val" \
+				${srcdir}/config/arm/arm-cpus.in`
+			  if [ "$cpu" = "error" ]; then
+			    echo "Unknown target in --with-$which=$val" 1>&2
+			    exit 1
+			  else
+			    new_val=$cpu
+			    eval "target_${which}_cname=$new_val"
+			    echo "For $val real value is $new_val"
 			  fi
-			  true
-			else
-			  echo "Unknown CPU used in --with-$which=$val" 1>&2
-			  exit 1
 			fi
 		done
 
-		# See if it matches any of the entries in arm-arches.def
-		if [ x"$with_arch" = x ] \
-		    || grep "^ARM_ARCH(\"$with_arch\"," \
-			    ${srcdir}/config/arm/arm-arches.def \
-			    > /dev/null; then
-		  # OK
-		  true
-		else
-		  echo "Unknown arch used in --with-arch=$with_arch" 1>&2
-		  exit 1
-		fi
-
 		case "$with_float" in
 		"" \
 		| soft | hard | softfp)
@@ -3706,16 +3689,16 @@ case "${target}" in
 			;;
 		esac
 
-		# see if it matches any of the entries in arm-fpus.def
-		if [ x"$with_fpu" = x ] \
-		    || grep "^ARM_FPU(\"$with_fpu\"," \
-			    ${srcdir}/config/arm/arm-fpus.def \
-			    > /dev/null; then
-		  # OK
-		  true
-		else
-		  echo "Unknown fpu used in --with-fpu=$with_fpu" 1>&2
-		  exit 1
+		# see if --with-fpu matches any of the supported FPUs
+		if [ x"$with_fpu" != x ] ; then
+		  fpu=`awk -f ${srcdir}/config/arm/parsecpu.awk \
+			-v cmd="chkfpu $with_fpu" \
+			${srcdir}/config/arm/arm-cpus.in`
+		  if [ "$fpu" = "error"]
+		  then
+		    echo "Unknown target in --with-$which=$val" 1>&2
+		    exit 1
+		  fi
 		fi
 
 		case "$with_abi" in
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
deleted file mode 100644
index 268de95..0000000
--- a/gcc/config/arm/arm-arches.def
+++ /dev/null
@@ -1,67 +0,0 @@
-/* ARM CPU architectures.
-   Copyright (C) 1991-2017 Free Software Foundation, Inc.
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-/* Before using #include to read this file, define a macro:
-
-      ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)
-
-   The NAME is the name of the architecture, represented as a string
-   constant.  The CORE is the identifier for a core representative of
-   this architecture.  ARCH is the architecture revision.  ISA is the
-   detailed architectural capabilities of the core (see arm-isa.h).
-
-   genopt.sh assumes no whitespace up to the first "," in each entry.  */
-
-ARM_ARCH("armv2",   arm2,	(TF_CO_PROC | TF_NO_MODE32), 2,		ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
-ARM_ARCH("armv2a",  arm2,	(TF_CO_PROC | TF_NO_MODE32), 2,		ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
-ARM_ARCH("armv3",   arm6,	TF_CO_PROC,		     3,		ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26))
-ARM_ARCH("armv3m",  arm7m,	TF_CO_PROC,		     3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26))
-ARM_ARCH("armv4",   arm7tdmi,	TF_CO_PROC,		     4,		ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26))
-/* Strictly, isa_bit_mode26 is a permitted option for v4t, but there are no
-   implementations that support it, so we will leave it out for now.  */
-ARM_ARCH("armv4t",  arm7tdmi,	TF_CO_PROC,		     4T,	ISA_FEAT(ISA_ARMv4t))
-ARM_ARCH("armv5",   arm10tdmi,	TF_CO_PROC,		     5,		ISA_FEAT(ISA_ARMv5))
-ARM_ARCH("armv5t",  arm10tdmi,	TF_CO_PROC,		     5T,	ISA_FEAT(ISA_ARMv5t))
-ARM_ARCH("armv5e",  arm1026ejs, TF_CO_PROC,		     5E,	ISA_FEAT(ISA_ARMv5e))
-ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC,		     5TE,	ISA_FEAT(ISA_ARMv5te))
-ARM_ARCH("armv6",   arm1136js,	TF_CO_PROC,		     6,		ISA_FEAT(ISA_ARMv6))
-ARM_ARCH("armv6j",  arm1136js,	TF_CO_PROC,		     6J,	ISA_FEAT(ISA_ARMv6j))
-ARM_ARCH("armv6k",  mpcore,	TF_CO_PROC,		     6K,	ISA_FEAT(ISA_ARMv6k))
-ARM_ARCH("armv6z",  arm1176jzs, TF_CO_PROC,		     6Z,	ISA_FEAT(ISA_ARMv6z))
-ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC,		     6KZ,	ISA_FEAT(ISA_ARMv6kz))
-ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC,		     6KZ,	ISA_FEAT(ISA_ARMv6kz))
-ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC,		     6T2,	ISA_FEAT(ISA_ARMv6t2))
-ARM_ARCH("armv6-m", cortexm1,	0,			     6M,	ISA_FEAT(ISA_ARMv6m))
-ARM_ARCH("armv6s-m", cortexm1,	0,			     6M,	ISA_FEAT(ISA_ARMv6m))
-ARM_ARCH("armv7",   cortexa8,	TF_CO_PROC,		     7,		ISA_FEAT(ISA_ARMv7))
-ARM_ARCH("armv7-a", cortexa8,	TF_CO_PROC,		     7A,	ISA_FEAT(ISA_ARMv7a))
-ARM_ARCH("armv7ve", cortexa8,	TF_CO_PROC,		     7A,	ISA_FEAT(ISA_ARMv7ve))
-ARM_ARCH("armv7-r", cortexr4,	TF_CO_PROC,		     7R,	ISA_FEAT(ISA_ARMv7r))
-ARM_ARCH("armv7-m", cortexm3,	TF_CO_PROC,		     7M,	ISA_FEAT(ISA_ARMv7m))
-ARM_ARCH("armv7e-m", cortexm4,	TF_CO_PROC,		     7EM,	ISA_FEAT(ISA_ARMv7em))
-ARM_ARCH("armv8-a", cortexa53,	TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8a))
-ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32))
-ARM_ARCH("armv8.1-a", cortexa53,  TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8_1a))
-ARM_ARCH ("armv8.2-a", cortexa53,  TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8_2a))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC,	     8A,	ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16))
-ARM_ARCH("armv8-m.base", cortexm23, 0,			     8M_BASE,	ISA_FEAT(ISA_ARMv8m_base))
-ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC,		     8M_MAIN,	ISA_FEAT(ISA_ARMv8m_main))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC,	     8M_MAIN,	ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em))
-ARM_ARCH("iwmmxt",  iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt))
-ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
deleted file mode 100644
index ef587df..0000000
--- a/gcc/config/arm/arm-cores.def
+++ /dev/null
@@ -1,188 +0,0 @@
-/* ARM CPU Cores
-   Copyright (C) 2003-2017 Free Software Foundation, Inc.
-   Written by CodeSourcery, LLC
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3, or (at your option)
-   any later version.
-
-   GCC is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
-
-   Under Section 7 of GPL version 3, you are granted additional
-   permissions described in the GCC Runtime Library Exception, version
-   3.1, as published by the Free Software Foundation.
-
-   You should have received a copy of the GNU General Public License and
-   a copy of the GCC Runtime Library Exception along with this program;
-   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-   <http://www.gnu.org/licenses/>.  */
-
-/* Before using #include to read this file, define a macro:
-
-      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)
-
-   The CORE_NAME is the name of the core, represented as a string constant.
-   The INTERNAL_IDENT is the name of the core represented as an identifier.
-   This must be unique for each entry in this table.
-   The TUNE_IDENT is the name of the core for which scheduling decisions
-   should be made, represented as an identifier.
-   TUNE_FLAGS is a set of flag bits that are used to affect tuning.
-   ARCH is the architecture revision implemented by the chip.
-   ISA is the detailed architectural capabilities of the core (see arm-isa.h).
-   COSTS is the name of the rtx_costs routine to use.
-
-   If you update this table, you must update the "tune" attribute in
-   arm.md.
-   
-   Some tools assume no whitespace up to the first "," in each entry.  */
-
-/* V2/V2A Architecture Processors */
-ARM_CORE("arm2",	arm2, arm2,		(TF_CO_PROC | TF_NO_MODE32),	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm250",	arm250, arm250,		(TF_CO_PROC | TF_NO_MODE32),	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm3",	arm3, arm3,		(TF_CO_PROC | TF_NO_MODE32),	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
-
-/* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm60",	arm60, arm60,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm600",	arm600, arm600,		(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm610",	arm610, arm610,		TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm620",	arm620, arm620,		(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm7",	arm7, arm7,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm70",	arm70, arm70,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm700",	arm700, arm700,		(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm710",	arm710, arm710,		TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm720",	arm720, arm720,		TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	TF_WBUF,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-/* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
-
-/* V3M Architecture Processors */
-/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
-   those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,		TF_CO_PROC,			  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,		TF_CO_PROC,			  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,		TF_CO_PROC,			  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
-
-/* V4 Architecture Processors */
-ARM_CORE("arm8",	  arm8, arm8,			TF_LDSCHED,		  4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
-ARM_CORE("arm810",	  arm810, arm810,		TF_LDSCHED,		  4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
-ARM_CORE("strongarm",	  strongarm, strongarm,		(TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	(TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
-ARM_CORE("fa526",	  fa526, fa526,			TF_LDSCHED,		  4,	ISA_FEAT(ISA_ARMv4), fastmul)
-ARM_CORE("fa626",	  fa626, fa626,			TF_LDSCHED,		  4,	ISA_FEAT(ISA_ARMv4), fastmul)
-
-/* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	TF_CO_PROC,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	TF_CO_PROC,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	TF_WBUF,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	TF_WBUF,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	TF_WBUF,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm9",	arm9, arm9,		TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm920",	arm920, arm920,		TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		TF_LDSCHED,			  4T,	ISA_FEAT(ISA_ARMv4t), fastmul)
-
-/* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	TF_LDSCHED,			  5T,	ISA_FEAT(ISA_ARMv5t), fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	TF_LDSCHED,			  5T,	ISA_FEAT(ISA_ARMv5t), fastmul)
-
-/* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), fastmul)
-ARM_CORE("xscale",	xscale, xscale,		(TF_LDSCHED | TF_XSCALE),	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		(TF_LDSCHED | TF_XSCALE),	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	(TF_LDSCHED | TF_XSCALE),	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), fa726te)
-
-/* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	TF_LDSCHED,			  5TEJ,	ISA_FEAT(ISA_ARMv5tej), 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	TF_LDSCHED,			  5TEJ,	ISA_FEAT(ISA_ARMv5tej), 9e)
-
-/* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		TF_LDSCHED,	  6J,	ISA_FEAT(ISA_ARMv6j), 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		TF_LDSCHED,	  6J,	ISA_FEAT(ISA_ARMv6j) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		TF_LDSCHED,	  6KZ,	ISA_FEAT(ISA_ARMv6kz), 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	TF_LDSCHED,	  6KZ,	ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	TF_LDSCHED,	  6K,	ISA_FEAT(ISA_ARMv6k), 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			TF_LDSCHED,	  6K,	ISA_FEAT(ISA_ARMv6k) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		TF_LDSCHED,	  6T2,	ISA_FEAT(ISA_ARMv6t2), v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	TF_LDSCHED,	  6T2,	ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), v6t2)
-
-/* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		TF_LDSCHED,	  6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		TF_LDSCHED,	  6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	TF_LDSCHED,	  6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-
-/* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	(TF_LDSCHED | TF_SMALLMUL),  6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	(TF_LDSCHED | TF_SMALLMUL),  6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M,	ISA_FEAT(ISA_ARMv6m), v6m)
-
-/* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), cortex_a9)
-ARM_CORE("cortex-a12",		cortexa12, cortexa17,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7ve), cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7ve), cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		TF_LDSCHED,	  7R,	ISA_FEAT(ISA_ARMv7r), cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		TF_LDSCHED,	  7R,	ISA_FEAT(ISA_ARMv7r), cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		TF_LDSCHED,	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		TF_LDSCHED,	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
-ARM_CORE("cortex-r8",		cortexr8, cortexr7,		TF_LDSCHED,	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		TF_LDSCHED,	  7EM,	ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		TF_LDSCHED,	  7EM,	ISA_FEAT(ISA_ARMv7em), v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		TF_LDSCHED,	  7M,	ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), marvell_pj4)
-
-/* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7ve), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7ve), cortex_a12)
-
-/* V8 A-profile Architecture Processors */
-ARM_CORE("cortex-a32",	cortexa32, cortexa53,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
-ARM_CORE("cortex-a35",	cortexa35, cortexa53,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
-ARM_CORE("cortex-a73",	cortexa73, cortexa57,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
-ARM_CORE("exynos-m1",	exynosm1,  exynosm1,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), exynosm1)
-ARM_CORE("falkor",	falkor,	   cortexa57,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
-ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
-ARM_CORE("xgene1",	xgene1,	   xgene1,	TF_LDSCHED,			  8A,	ISA_FEAT(ISA_ARMv8a), xgene1)
-
-/* V8 A-profile big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED,	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED,	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED,	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED,	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
-
-/* V8 M-profile implementations.  */
-ARM_CORE("cortex-m23",	cortexm23, cortexm23,	TF_LDSCHED,			  8M_BASE, ISA_FEAT(ISA_ARMv8m_base), v6m)
-ARM_CORE("cortex-m33",	cortexm33, cortexm33,	TF_LDSCHED,			  8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), v7m)
diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
new file mode 100644
index 0000000..b388812
--- /dev/null
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -0,0 +1,1058 @@
+/* -*- buffer-read-only: t -*-
+   Generated automatically by parsecpu.awk from arm-cpus.in.
+   Do not edit.
+
+   Copyright (C) 2011-2017 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public
+   License along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+static const struct arm_arch_core_flag arm_arch_core_flags[] =
+{
+  {
+    "arm2",
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm250",
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm3",
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm6",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm60",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm600",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm610",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm620",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7d",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7di",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm70",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm700",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm700i",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm710",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm720",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm710c",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7100",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7500",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7500fe",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7m",
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7dm",
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7dmi",
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm8",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm810",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "strongarm",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "strongarm110",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "strongarm1100",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "strongarm1110",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "fa526",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "fa626",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "arm7tdmi",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm7tdmi-s",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm710t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm720t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm740t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm9",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm9tdmi",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm920",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm920t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm922t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm940t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "ep9312",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "arm10tdmi",
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+  },
+  {
+    "arm1020t",
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+  },
+  {
+    "arm9e",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm946e-s",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm966e-s",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm968e-s",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm10e",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm1020e",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm1022e",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "xscale",
+    {
+      ISA_ARMv5te,
+      isa_bit_xscale,
+      isa_nobit
+    },
+  },
+  {
+    "iwmmxt",
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+  },
+  {
+    "iwmmxt2",
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+  },
+  {
+    "fa606te",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "fa626te",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "fmp626",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "fa726te",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "arm926ej-s",
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+  },
+  {
+    "arm1026ej-s",
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+  },
+  {
+    "arm1136j-s",
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+  },
+  {
+    "arm1136jf-s",
+    {
+      ISA_ARMv6j,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+  },
+  {
+    "arm1176jz-s",
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+  },
+  {
+    "arm1176jzf-s",
+    {
+      ISA_ARMv6kz,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+  },
+  {
+    "mpcorenovfp",
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+  },
+  {
+    "mpcore",
+    {
+      ISA_ARMv6k,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+  },
+  {
+    "arm1156t2-s",
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+  },
+  {
+    "arm1156t2f-s",
+    {
+      ISA_ARMv6t2,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m1",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m0",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m0plus",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m1.small-multiply",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m0.small-multiply",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m0plus.small-multiply",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "generic-armv7-a",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a5",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a7",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a8",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a9",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a12",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a15",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a17",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-r4",
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-r4f",
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-r5",
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-r7",
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-r8",
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m7",
+    {
+      ISA_ARMv7em,
+      isa_quirk_no_volatile_ce,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m4",
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m3",
+    {
+      ISA_ARMv7m,
+      isa_quirk_cm3_ldrd,
+      isa_nobit
+    },
+  },
+  {
+    "marvell-pj4",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a15.cortex-a7",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a17.cortex-a7",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a32",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a35",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a53",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a57",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a72",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a73",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "exynos-m1",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "falkor",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "qdf24xx",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "xgene1",
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a57.cortex-a53",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a72.cortex-a53",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a73.cortex-a35",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-a73.cortex-a53",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m23",
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+  },
+  {
+    "cortex-m33",
+    {
+      ISA_ARMv8m_main,isa_bit_ARMv7em,
+      isa_nobit
+    },
+  },
+  {
+    "armv2",
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "armv2a",
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "armv3",
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "armv3m",
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "armv4",
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+  },
+  {
+    "armv4t",
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+  },
+  {
+    "armv5",
+    {
+      ISA_ARMv5,
+      isa_nobit
+    },
+  },
+  {
+    "armv5t",
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+  },
+  {
+    "armv5e",
+    {
+      ISA_ARMv5e,
+      isa_nobit
+    },
+  },
+  {
+    "armv5te",
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+  },
+  {
+    "armv5tej",
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+  },
+  {
+    "armv6",
+    {
+      ISA_ARMv6,
+      isa_nobit
+    },
+  },
+  {
+    "armv6j",
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+  },
+  {
+    "armv6k",
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+  },
+  {
+    "armv6z",
+    {
+      ISA_ARMv6z,
+      isa_nobit
+    },
+  },
+  {
+    "armv6kz",
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+  },
+  {
+    "armv6zk",
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+  },
+  {
+    "armv6t2",
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+  },
+  {
+    "armv6-m",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "armv6s-m",
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+  },
+  {
+    "armv7",
+    {
+      ISA_ARMv7,
+      isa_nobit
+    },
+  },
+  {
+    "armv7-a",
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+  },
+  {
+    "armv7ve",
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+  },
+  {
+    "armv7-r",
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+  },
+  {
+    "armv7-m",
+    {
+      ISA_ARMv7m,
+      isa_nobit
+    },
+  },
+  {
+    "armv7e-m",
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-a",
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-a+crc",
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
+    "armv8.1-a",
+    {
+      ISA_ARMv8_1a,
+      isa_nobit
+    },
+  },
+  {
+    "armv8.2-a",
+    {
+      ISA_ARMv8_2a,
+      isa_nobit
+    },
+  },
+  {
+    "armv8.2-a+fp16",
+    {
+      ISA_ARMv8_2a,isa_bit_fp16,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-m.base",
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-m.main",
+    {
+      ISA_ARMv8m_main,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-m.main+dsp",
+    {
+      ISA_ARMv8m_main,isa_bit_ARMv7em,
+      isa_nobit
+    },
+  },
+  {
+    "iwmmxt",
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+  },
+  {
+    "iwmmxt2",
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+  },
+};
+
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
new file mode 100644
index 0000000..d6200f9
--- /dev/null
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -0,0 +1,1652 @@
+/* -*- buffer-read-only: t -*-
+   Generated automatically by parsecpu.awk from arm-cpus.in.
+   Do not edit.
+
+   Copyright (C) 2011-2017 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public
+   License along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+static const struct processors all_cores[] =
+{
+  {
+    "arm2", TARGET_CPU_arm2,
+    (TF_CO_PROC | TF_NO_MODE32),
+    "2", BASE_ARCH_2,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm250", TARGET_CPU_arm250,
+    (TF_CO_PROC | TF_NO_MODE32),
+    "2", BASE_ARCH_2,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm3", TARGET_CPU_arm3,
+    (TF_CO_PROC | TF_NO_MODE32),
+    "2", BASE_ARCH_2,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm6", TARGET_CPU_arm6,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm60", TARGET_CPU_arm60,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm600", TARGET_CPU_arm600,
+    (TF_CO_PROC | TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm610", TARGET_CPU_arm610,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm620", TARGET_CPU_arm620,
+    (TF_CO_PROC | TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7", TARGET_CPU_arm7,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7d", TARGET_CPU_arm7d,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7di", TARGET_CPU_arm7di,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm70", TARGET_CPU_arm70,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm700", TARGET_CPU_arm700,
+    (TF_CO_PROC | TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm700i", TARGET_CPU_arm700i,
+    (TF_CO_PROC | TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm710", TARGET_CPU_arm710,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm720", TARGET_CPU_arm720,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm710c", TARGET_CPU_arm710c,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7100", TARGET_CPU_arm7100,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7500", TARGET_CPU_arm7500,
+    (TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7500fe", TARGET_CPU_arm7500fe,
+    (TF_CO_PROC | TF_WBUF),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_slowmul_tune
+  },
+  {
+    "arm7m", TARGET_CPU_arm7m,
+    (TF_CO_PROC),
+    "3M", BASE_ARCH_3M,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm7dm", TARGET_CPU_arm7dm,
+    (TF_CO_PROC),
+    "3M", BASE_ARCH_3M,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm7dmi", TARGET_CPU_arm7dmi,
+    (TF_CO_PROC),
+    "3M", BASE_ARCH_3M,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm8", TARGET_CPU_arm8,
+    (TF_LDSCHED),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm810", TARGET_CPU_arm810,
+    (TF_LDSCHED),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "strongarm", TARGET_CPU_strongarm,
+    (TF_LDSCHED | TF_STRONG),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_strongarm_tune
+  },
+  {
+    "strongarm110", TARGET_CPU_strongarm110,
+    (TF_LDSCHED | TF_STRONG),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_strongarm_tune
+  },
+  {
+    "strongarm1100", TARGET_CPU_strongarm1100,
+    (TF_LDSCHED | TF_STRONG),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_strongarm_tune
+  },
+  {
+    "strongarm1110", TARGET_CPU_strongarm1110,
+    (TF_LDSCHED | TF_STRONG),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_strongarm_tune
+  },
+  {
+    "fa526", TARGET_CPU_fa526,
+    (TF_LDSCHED),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "fa626", TARGET_CPU_fa626,
+    (TF_LDSCHED),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm7tdmi", TARGET_CPU_arm7tdmi,
+    (TF_CO_PROC),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm7tdmi-s", TARGET_CPU_arm7tdmis,
+    (TF_CO_PROC),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm710t", TARGET_CPU_arm710t,
+    (TF_WBUF),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm720t", TARGET_CPU_arm720t,
+    (TF_WBUF),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm740t", TARGET_CPU_arm740t,
+    (TF_WBUF),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm9", TARGET_CPU_arm9,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm9tdmi", TARGET_CPU_arm9tdmi,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm920", TARGET_CPU_arm920,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm920t", TARGET_CPU_arm920t,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm922t", TARGET_CPU_arm922t,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm940t", TARGET_CPU_arm940t,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "ep9312", TARGET_CPU_ep9312,
+    (TF_LDSCHED),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm10tdmi", TARGET_CPU_arm10tdmi,
+    (TF_LDSCHED),
+    "5T", BASE_ARCH_5T,
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm1020t", TARGET_CPU_arm1020t,
+    (TF_LDSCHED),
+    "5T", BASE_ARCH_5T,
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm9e", TARGET_CPU_arm9e,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm946e-s", TARGET_CPU_arm946es,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm966e-s", TARGET_CPU_arm966es,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm968e-s", TARGET_CPU_arm968es,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm10e", TARGET_CPU_arm10e,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm1020e", TARGET_CPU_arm1020e,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "arm1022e", TARGET_CPU_arm1022e,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_fastmul_tune
+  },
+  {
+    "xscale", TARGET_CPU_xscale,
+    (TF_LDSCHED | TF_XSCALE),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_bit_xscale,
+      isa_nobit
+    },
+    &arm_xscale_tune
+  },
+  {
+    "iwmmxt", TARGET_CPU_iwmmxt,
+    (TF_LDSCHED | TF_XSCALE),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+    &arm_xscale_tune
+  },
+  {
+    "iwmmxt2", TARGET_CPU_iwmmxt2,
+    (TF_LDSCHED | TF_XSCALE),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+    &arm_xscale_tune
+  },
+  {
+    "fa606te", TARGET_CPU_fa606te,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "fa626te", TARGET_CPU_fa626te,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "fmp626", TARGET_CPU_fmp626,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "fa726te", TARGET_CPU_fa726te,
+    (TF_LDSCHED),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    &arm_fa726te_tune
+  },
+  {
+    "arm926ej-s", TARGET_CPU_arm926ejs,
+    (TF_LDSCHED),
+    "5TEJ", BASE_ARCH_5TEJ,
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1026ej-s", TARGET_CPU_arm1026ejs,
+    (TF_LDSCHED),
+    "5TEJ", BASE_ARCH_5TEJ,
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1136j-s", TARGET_CPU_arm1136js,
+    (TF_LDSCHED),
+    "6J", BASE_ARCH_6J,
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1136jf-s", TARGET_CPU_arm1136jfs,
+    (TF_LDSCHED),
+    "6J", BASE_ARCH_6J,
+    {
+      ISA_ARMv6j,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1176jz-s", TARGET_CPU_arm1176jzs,
+    (TF_LDSCHED),
+    "6KZ", BASE_ARCH_6KZ,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1176jzf-s", TARGET_CPU_arm1176jzfs,
+    (TF_LDSCHED),
+    "6KZ", BASE_ARCH_6KZ,
+    {
+      ISA_ARMv6kz,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "mpcorenovfp", TARGET_CPU_mpcorenovfp,
+    (TF_LDSCHED),
+    "6K", BASE_ARCH_6K,
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "mpcore", TARGET_CPU_mpcore,
+    (TF_LDSCHED),
+    "6K", BASE_ARCH_6K,
+    {
+      ISA_ARMv6k,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+    &arm_9e_tune
+  },
+  {
+    "arm1156t2-s", TARGET_CPU_arm1156t2s,
+    (TF_LDSCHED),
+    "6T2", BASE_ARCH_6T2,
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+    &arm_v6t2_tune
+  },
+  {
+    "arm1156t2f-s", TARGET_CPU_arm1156t2fs,
+    (TF_LDSCHED),
+    "6T2", BASE_ARCH_6T2,
+    {
+      ISA_ARMv6t2,
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    },
+    &arm_v6t2_tune
+  },
+  {
+    "cortex-m1", TARGET_CPU_cortexm1,
+    (TF_LDSCHED),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m0", TARGET_CPU_cortexm0,
+    (TF_LDSCHED),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m0plus", TARGET_CPU_cortexm0plus,
+    (TF_LDSCHED),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m1.small-multiply", TARGET_CPU_cortexm1smallmultiply,
+    (TF_LDSCHED | TF_SMALLMUL),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m0.small-multiply", TARGET_CPU_cortexm0smallmultiply,
+    (TF_LDSCHED | TF_SMALLMUL),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m0plus.small-multiply", TARGET_CPU_cortexm0plussmallmultiply,
+    (TF_LDSCHED | TF_SMALLMUL),
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "generic-armv7-a", TARGET_CPU_genericv7a,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-a5", TARGET_CPU_cortexa5,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    &arm_cortex_a5_tune
+  },
+  {
+    "cortex-a7", TARGET_CPU_cortexa7,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a7_tune
+  },
+  {
+    "cortex-a8", TARGET_CPU_cortexa8,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    &arm_cortex_a8_tune
+  },
+  {
+    "cortex-a9", TARGET_CPU_cortexa9,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    &arm_cortex_a9_tune
+  },
+  {
+    "cortex-a12", TARGET_CPU_cortexa12,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a12_tune
+  },
+  {
+    "cortex-a15", TARGET_CPU_cortexa15,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a15_tune
+  },
+  {
+    "cortex-a17", TARGET_CPU_cortexa17,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a12_tune
+  },
+  {
+    "cortex-r4", TARGET_CPU_cortexr4,
+    (TF_LDSCHED),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-r4f", TARGET_CPU_cortexr4f,
+    (TF_LDSCHED),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-r5", TARGET_CPU_cortexr5,
+    (TF_LDSCHED),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-r7", TARGET_CPU_cortexr7,
+    (TF_LDSCHED),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-r8", TARGET_CPU_cortexr8,
+    (TF_LDSCHED),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_bit_adiv,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
+  {
+    "cortex-m7", TARGET_CPU_cortexm7,
+    (TF_LDSCHED),
+    "7EM", BASE_ARCH_7EM,
+    {
+      ISA_ARMv7em,
+      isa_quirk_no_volatile_ce,
+      isa_nobit
+    },
+    &arm_cortex_m7_tune
+  },
+  {
+    "cortex-m4", TARGET_CPU_cortexm4,
+    (TF_LDSCHED),
+    "7EM", BASE_ARCH_7EM,
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+    &arm_v7m_tune
+  },
+  {
+    "cortex-m3", TARGET_CPU_cortexm3,
+    (TF_LDSCHED),
+    "7M", BASE_ARCH_7M,
+    {
+      ISA_ARMv7m,
+      isa_quirk_cm3_ldrd,
+      isa_nobit
+    },
+    &arm_v7m_tune
+  },
+  {
+    "marvell-pj4", TARGET_CPU_marvell_pj4,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    &arm_marvell_pj4_tune
+  },
+  {
+    "cortex-a15.cortex-a7", TARGET_CPU_cortexa15cortexa7,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a15_tune
+  },
+  {
+    "cortex-a17.cortex-a7", TARGET_CPU_cortexa17cortexa7,
+    (TF_LDSCHED),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    &arm_cortex_a12_tune
+  },
+  {
+    "cortex-a32", TARGET_CPU_cortexa32,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a35_tune
+  },
+  {
+    "cortex-a35", TARGET_CPU_cortexa35,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a35_tune
+  },
+  {
+    "cortex-a53", TARGET_CPU_cortexa53,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a53_tune
+  },
+  {
+    "cortex-a57", TARGET_CPU_cortexa57,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a57_tune
+  },
+  {
+    "cortex-a72", TARGET_CPU_cortexa72,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a57_tune
+  },
+  {
+    "cortex-a73", TARGET_CPU_cortexa73,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a73_tune
+  },
+  {
+    "exynos-m1", TARGET_CPU_exynosm1,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_exynosm1_tune
+  },
+  {
+    "falkor", TARGET_CPU_falkor,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_qdf24xx_tune
+  },
+  {
+    "qdf24xx", TARGET_CPU_qdf24xx,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_qdf24xx_tune
+  },
+  {
+    "xgene1", TARGET_CPU_xgene1,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+    &arm_xgene1_tune
+  },
+  {
+    "cortex-a57.cortex-a53", TARGET_CPU_cortexa57cortexa53,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a57_tune
+  },
+  {
+    "cortex-a72.cortex-a53", TARGET_CPU_cortexa72cortexa53,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a57_tune
+  },
+  {
+    "cortex-a73.cortex-a35", TARGET_CPU_cortexa73cortexa35,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a73_tune
+  },
+  {
+    "cortex-a73.cortex-a53", TARGET_CPU_cortexa73cortexa53,
+    (TF_LDSCHED),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_a73_tune
+  },
+  {
+    "cortex-m23", TARGET_CPU_cortexm23,
+    (TF_LDSCHED),
+    "8M_BASE", BASE_ARCH_8M_BASE,
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+    &arm_v6m_tune
+  },
+  {
+    "cortex-m33", TARGET_CPU_cortexm33,
+    (TF_LDSCHED),
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    {
+      ISA_ARMv8m_main,isa_bit_ARMv7em,
+      isa_nobit
+    },
+    &arm_v7m_tune
+  },
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
+};
+
+static const struct processors all_architectures[] =
+{
+  {
+    "armv2", TARGET_CPU_arm2,
+    (TF_CO_PROC | TF_NO_MODE32),
+    "2", BASE_ARCH_2,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv2a", TARGET_CPU_arm2,
+    (TF_CO_PROC | TF_NO_MODE32),
+    "2", BASE_ARCH_2,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv3", TARGET_CPU_arm6,
+    (TF_CO_PROC),
+    "3", BASE_ARCH_3,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv3m", TARGET_CPU_arm7m,
+    (TF_CO_PROC),
+    "3M", BASE_ARCH_3M,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv4", TARGET_CPU_arm7tdmi,
+    (TF_CO_PROC),
+    "4", BASE_ARCH_4,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv4t", TARGET_CPU_arm7tdmi,
+    (TF_CO_PROC),
+    "4T", BASE_ARCH_4T,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv5", TARGET_CPU_arm10tdmi,
+    (TF_CO_PROC),
+    "5", BASE_ARCH_5,
+    {
+      ISA_ARMv5,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv5t", TARGET_CPU_arm10tdmi,
+    (TF_CO_PROC),
+    "5T", BASE_ARCH_5T,
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv5e", TARGET_CPU_arm1026ejs,
+    (TF_CO_PROC),
+    "5E", BASE_ARCH_5E,
+    {
+      ISA_ARMv5e,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv5te", TARGET_CPU_arm1026ejs,
+    (TF_CO_PROC),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv5tej", TARGET_CPU_arm1026ejs,
+    (TF_CO_PROC),
+    "5TEJ", BASE_ARCH_5TEJ,
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6", TARGET_CPU_arm1136js,
+    (TF_CO_PROC),
+    "6", BASE_ARCH_6,
+    {
+      ISA_ARMv6,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6j", TARGET_CPU_arm1136js,
+    (TF_CO_PROC),
+    "6J", BASE_ARCH_6J,
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6k", TARGET_CPU_mpcore,
+    (TF_CO_PROC),
+    "6K", BASE_ARCH_6K,
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6z", TARGET_CPU_arm1176jzs,
+    (TF_CO_PROC),
+    "6Z", BASE_ARCH_6Z,
+    {
+      ISA_ARMv6z,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6kz", TARGET_CPU_arm1176jzs,
+    (TF_CO_PROC),
+    "6KZ", BASE_ARCH_6KZ,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6zk", TARGET_CPU_arm1176jzs,
+    (TF_CO_PROC),
+    "6KZ", BASE_ARCH_6KZ,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6t2", TARGET_CPU_arm1156t2s,
+    (TF_CO_PROC),
+    "6T2", BASE_ARCH_6T2,
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6-m", TARGET_CPU_cortexm1,
+    0,
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv6s-m", TARGET_CPU_cortexm1,
+    0,
+    "6M", BASE_ARCH_6M,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7", TARGET_CPU_cortexa8,
+    (TF_CO_PROC),
+    "7", BASE_ARCH_7,
+    {
+      ISA_ARMv7,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7-a", TARGET_CPU_cortexa8,
+    (TF_CO_PROC),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7ve", TARGET_CPU_cortexa8,
+    (TF_CO_PROC),
+    "7A", BASE_ARCH_7A,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7-r", TARGET_CPU_cortexr4,
+    (TF_CO_PROC),
+    "7R", BASE_ARCH_7R,
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7-m", TARGET_CPU_cortexm3,
+    (TF_CO_PROC),
+    "7M", BASE_ARCH_7M,
+    {
+      ISA_ARMv7m,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv7e-m", TARGET_CPU_cortexm4,
+    (TF_CO_PROC),
+    "7EM", BASE_ARCH_7EM,
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-a", TARGET_CPU_cortexa53,
+    (TF_CO_PROC),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-a+crc", TARGET_CPU_cortexa53,
+    (TF_CO_PROC),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8a,isa_bit_crc32,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8.1-a", TARGET_CPU_cortexa53,
+    (TF_CO_PROC),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8_1a,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8.2-a", TARGET_CPU_cortexa53,
+    (TF_CO_PROC),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8_2a,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8.2-a+fp16", TARGET_CPU_cortexa53,
+    (TF_CO_PROC),
+    "8A", BASE_ARCH_8A,
+    {
+      ISA_ARMv8_2a,isa_bit_fp16,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-m.base", TARGET_CPU_cortexm23,
+    0,
+    "8M_BASE", BASE_ARCH_8M_BASE,
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-m.main", TARGET_CPU_cortexm7,
+    (TF_CO_PROC),
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    {
+      ISA_ARMv8m_main,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-m.main+dsp", TARGET_CPU_cortexm33,
+    (TF_CO_PROC),
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    {
+      ISA_ARMv8m_main,isa_bit_ARMv7em,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "iwmmxt", TARGET_CPU_iwmmxt,
+    (TF_LDSCHED | TF_STRONG | TF_XSCALE),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "iwmmxt2", TARGET_CPU_iwmmxt2,
+    (TF_LDSCHED | TF_STRONG | TF_XSCALE),
+    "5TE", BASE_ARCH_5TE,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+    NULL
+  },
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
+};
+
+const struct arm_fpu_desc all_fpus[] =
+{
+  {
+    "vfp",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv2",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-fp16",
+    {
+      ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16-fp16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd",
+    {
+      ISA_VFPv3,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd-fp16",
+    {
+      ISA_VFPv3,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "neon",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv3",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp16",
+    {
+      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4",
+    {
+      ISA_VFPv4,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv4",
+    {
+      ISA_VFPv4,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4-d16",
+    {
+      ISA_VFPv4,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fpv4-sp-d16",
+    {
+      ISA_VFPv4,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-sp-d16",
+    {
+      ISA_FPv5,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-d16",
+    {
+      ISA_FPv5,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "crypto-neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_CRYPTO,
+      isa_nobit
+    }
+  },
+  {
+    "vfp3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+};
diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h
new file mode 100644
index 0000000..cd282db
--- /dev/null
+++ b/gcc/config/arm/arm-cpu.h
@@ -0,0 +1,162 @@
+/* -*- buffer-read-only: t -*-
+   Generated automatically by parsecpu.awk from arm-cpus.in.
+   Do not edit.
+
+   Copyright (C) 2011-2017 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public
+   License along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+enum processor_type
+{
+  TARGET_CPU_arm2,
+  TARGET_CPU_arm250,
+  TARGET_CPU_arm3,
+  TARGET_CPU_arm6,
+  TARGET_CPU_arm60,
+  TARGET_CPU_arm600,
+  TARGET_CPU_arm610,
+  TARGET_CPU_arm620,
+  TARGET_CPU_arm7,
+  TARGET_CPU_arm7d,
+  TARGET_CPU_arm7di,
+  TARGET_CPU_arm70,
+  TARGET_CPU_arm700,
+  TARGET_CPU_arm700i,
+  TARGET_CPU_arm710,
+  TARGET_CPU_arm720,
+  TARGET_CPU_arm710c,
+  TARGET_CPU_arm7100,
+  TARGET_CPU_arm7500,
+  TARGET_CPU_arm7500fe,
+  TARGET_CPU_arm7m,
+  TARGET_CPU_arm7dm,
+  TARGET_CPU_arm7dmi,
+  TARGET_CPU_arm8,
+  TARGET_CPU_arm810,
+  TARGET_CPU_strongarm,
+  TARGET_CPU_strongarm110,
+  TARGET_CPU_strongarm1100,
+  TARGET_CPU_strongarm1110,
+  TARGET_CPU_fa526,
+  TARGET_CPU_fa626,
+  TARGET_CPU_arm7tdmi,
+  TARGET_CPU_arm7tdmis,
+  TARGET_CPU_arm710t,
+  TARGET_CPU_arm720t,
+  TARGET_CPU_arm740t,
+  TARGET_CPU_arm9,
+  TARGET_CPU_arm9tdmi,
+  TARGET_CPU_arm920,
+  TARGET_CPU_arm920t,
+  TARGET_CPU_arm922t,
+  TARGET_CPU_arm940t,
+  TARGET_CPU_ep9312,
+  TARGET_CPU_arm10tdmi,
+  TARGET_CPU_arm1020t,
+  TARGET_CPU_arm9e,
+  TARGET_CPU_arm946es,
+  TARGET_CPU_arm966es,
+  TARGET_CPU_arm968es,
+  TARGET_CPU_arm10e,
+  TARGET_CPU_arm1020e,
+  TARGET_CPU_arm1022e,
+  TARGET_CPU_xscale,
+  TARGET_CPU_iwmmxt,
+  TARGET_CPU_iwmmxt2,
+  TARGET_CPU_fa606te,
+  TARGET_CPU_fa626te,
+  TARGET_CPU_fmp626,
+  TARGET_CPU_fa726te,
+  TARGET_CPU_arm926ejs,
+  TARGET_CPU_arm1026ejs,
+  TARGET_CPU_arm1136js,
+  TARGET_CPU_arm1136jfs,
+  TARGET_CPU_arm1176jzs,
+  TARGET_CPU_arm1176jzfs,
+  TARGET_CPU_mpcorenovfp,
+  TARGET_CPU_mpcore,
+  TARGET_CPU_arm1156t2s,
+  TARGET_CPU_arm1156t2fs,
+  TARGET_CPU_cortexm1,
+  TARGET_CPU_cortexm0,
+  TARGET_CPU_cortexm0plus,
+  TARGET_CPU_cortexm1smallmultiply,
+  TARGET_CPU_cortexm0smallmultiply,
+  TARGET_CPU_cortexm0plussmallmultiply,
+  TARGET_CPU_genericv7a,
+  TARGET_CPU_cortexa5,
+  TARGET_CPU_cortexa7,
+  TARGET_CPU_cortexa8,
+  TARGET_CPU_cortexa9,
+  TARGET_CPU_cortexa12,
+  TARGET_CPU_cortexa15,
+  TARGET_CPU_cortexa17,
+  TARGET_CPU_cortexr4,
+  TARGET_CPU_cortexr4f,
+  TARGET_CPU_cortexr5,
+  TARGET_CPU_cortexr7,
+  TARGET_CPU_cortexr8,
+  TARGET_CPU_cortexm7,
+  TARGET_CPU_cortexm4,
+  TARGET_CPU_cortexm3,
+  TARGET_CPU_marvell_pj4,
+  TARGET_CPU_cortexa15cortexa7,
+  TARGET_CPU_cortexa17cortexa7,
+  TARGET_CPU_cortexa32,
+  TARGET_CPU_cortexa35,
+  TARGET_CPU_cortexa53,
+  TARGET_CPU_cortexa57,
+  TARGET_CPU_cortexa72,
+  TARGET_CPU_cortexa73,
+  TARGET_CPU_exynosm1,
+  TARGET_CPU_falkor,
+  TARGET_CPU_qdf24xx,
+  TARGET_CPU_xgene1,
+  TARGET_CPU_cortexa57cortexa53,
+  TARGET_CPU_cortexa72cortexa53,
+  TARGET_CPU_cortexa73cortexa35,
+  TARGET_CPU_cortexa73cortexa53,
+  TARGET_CPU_cortexm23,
+  TARGET_CPU_cortexm33,
+  TARGET_CPU_arm_none
+};
+
+enum fpu_type
+{
+  TARGET_FPU_vfp,
+  TARGET_FPU_vfpv2,
+  TARGET_FPU_vfpv3,
+  TARGET_FPU_vfpv3_fp16,
+  TARGET_FPU_vfpv3_d16,
+  TARGET_FPU_vfpv3_d16_fp16,
+  TARGET_FPU_vfpv3xd,
+  TARGET_FPU_vfpv3xd_fp16,
+  TARGET_FPU_neon,
+  TARGET_FPU_neon_vfpv3,
+  TARGET_FPU_neon_fp16,
+  TARGET_FPU_vfpv4,
+  TARGET_FPU_neon_vfpv4,
+  TARGET_FPU_vfpv4_d16,
+  TARGET_FPU_fpv4_sp_d16,
+  TARGET_FPU_fpv5_sp_d16,
+  TARGET_FPU_fpv5_d16,
+  TARGET_FPU_fp_armv8,
+  TARGET_FPU_neon_fp_armv8,
+  TARGET_FPU_crypto_neon_fp_armv8,
+  TARGET_FPU_vfp3,
+  TARGET_FPU_auto
+};
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
new file mode 100644
index 0000000..fc5d935
--- /dev/null
+++ b/gcc/config/arm/arm-cpus.in
@@ -0,0 +1,1182 @@
+# CPU, FPU and architecture specifications for ARM.
+#
+# Copyright (C) 2011-2017 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# This file describes all the various CPUs, FPUs and architectures supported
+# by the compiler.  It is pre-processed by parsecpu.awk for a number of
+# purposes.
+#
+# The general form is a sequence of begin..end blocks with the following
+# syntax:
+# begin <object-type> <name>
+#  attribute-statement*
+# end <object-type> <name>
+#
+# where object type is one of "cpu" "arch" "fpu".  Each object type has
+# a specific set of permitted attributes, some of which are optional; further
+# details can be found below.
+#
+# Some objects cross-reference other objects by name.  Objects are permitted
+# in any order and it is not necessary to place a cross-referenced object
+# earlier in the file.
+#
+# The object names for cpu, arch and fpu objects are used for the public option
+# names in the final compiler.  The order within each group is preserved and
+# forms the order for the list within the compiler.
+
+# Architecture entries
+# format:
+# begin arch <name>
+#   tune for <cpu>
+#   [tune flags <list>]
+#   base <name>
+#   isa <isa-flags-list>
+# end arch <name>
+#
+
+begin arch armv2
+ tune for arm2
+ tune flags CO_PROC NO_MODE32
+ base 2
+ isa ARMv2 bit_mode26
+end arch armv2
+
+begin arch armv2a
+ tune for arm2
+ tune flags CO_PROC NO_MODE32
+ base 2
+ isa ARMv2 bit_mode26
+end arch armv2a
+
+begin arch armv3
+ tune for arm6
+ tune flags CO_PROC
+ base 3
+ isa ARMv3 bit_mode26
+end arch armv3
+
+begin arch armv3m
+ tune for arm7m
+ tune flags CO_PROC
+ base 3M
+ isa ARMv3m bit_mode26
+end arch armv3m
+
+begin arch armv4
+ tune for arm7tdmi
+ tune flags CO_PROC
+ base 4
+ isa ARMv4 bit_mode26
+end arch armv4
+
+# Strictly, bit_mode26 is a permitted option for v4t, but there are no
+# implementations that support it, so we will leave it out for now.
+begin arch armv4t
+ tune for arm7tdmi
+ tune flags CO_PROC
+ base 4T
+ isa ARMv4t
+end arch armv4t
+
+begin arch armv5
+ tune for arm10tdmi
+ tune flags CO_PROC
+ base 5
+ isa ARMv5
+end arch armv5
+
+begin arch armv5t
+ tune for arm10tdmi
+ tune flags CO_PROC
+ base 5T
+ isa ARMv5t
+end arch armv5t
+
+begin arch armv5e
+ tune for arm1026ej-s
+ tune flags CO_PROC
+ base 5E
+ isa ARMv5e
+end arch armv5e
+
+begin arch armv5te
+ tune for arm1026ej-s
+ tune flags CO_PROC
+ base 5TE
+ isa ARMv5te
+end arch armv5te
+
+begin arch armv5tej
+ tune for arm1026ej-s
+ tune flags CO_PROC
+ base 5TEJ
+ isa ARMv5tej
+end arch armv5tej
+
+begin arch armv6
+ tune for arm1136j-s
+ tune flags CO_PROC
+ base 6
+ isa ARMv6
+end arch armv6
+
+begin arch armv6j
+ tune for arm1136j-s
+ tune flags CO_PROC
+ base 6J
+ isa ARMv6j
+end arch armv6j
+
+begin arch armv6k
+ tune for mpcore
+ tune flags CO_PROC
+ base 6K
+ isa ARMv6k
+end arch armv6k
+
+begin arch armv6z
+ tune for arm1176jz-s
+ tune flags CO_PROC
+ base 6Z
+ isa ARMv6z
+end arch armv6z
+
+begin arch armv6kz
+ tune for arm1176jz-s
+ tune flags CO_PROC
+ base 6KZ
+ isa ARMv6kz
+end arch armv6kz
+
+begin arch armv6zk
+ tune for arm1176jz-s
+ tune flags CO_PROC
+ base 6KZ
+ isa ARMv6kz
+end arch armv6zk
+
+begin arch armv6t2
+ tune for arm1156t2-s
+ tune flags CO_PROC
+ base 6T2
+ isa ARMv6t2
+end arch armv6t2
+
+begin arch armv6-m
+ tune for cortex-m1
+ base 6M
+ isa ARMv6m
+end arch armv6-m
+
+begin arch armv6s-m
+ tune for cortex-m1
+ base 6M
+ isa ARMv6m
+end arch armv6s-m
+
+begin arch armv7
+ tune for cortex-a8
+ tune flags CO_PROC
+ base 7
+ isa ARMv7
+end arch armv7
+
+begin arch armv7-a
+ tune for cortex-a8
+ tune flags CO_PROC
+ base 7A
+ isa ARMv7a
+end arch armv7-a
+
+begin arch armv7ve
+ tune for cortex-a8
+ tune flags CO_PROC
+ base 7A
+ isa ARMv7ve
+end arch armv7ve
+
+begin arch armv7-r
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 7R
+ isa ARMv7r
+end arch armv7-r
+
+begin arch armv7-m
+ tune for cortex-m3
+ tune flags CO_PROC
+ base 7M
+ isa ARMv7m
+end arch armv7-m
+
+begin arch armv7e-m
+ tune for cortex-m4
+ tune flags CO_PROC
+ base 7EM
+ isa ARMv7em
+end arch armv7e-m
+
+begin arch armv8-a
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ isa ARMv8a
+end arch armv8-a
+
+begin arch armv8-a+crc
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ isa ARMv8a bit_crc32
+end arch armv8-a+crc
+
+begin arch armv8.1-a
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ isa ARMv8_1a
+end arch armv8.1-a
+
+begin arch armv8.2-a
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ isa ARMv8_2a
+end arch armv8.2-a
+
+begin arch armv8.2-a+fp16
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ isa ARMv8_2a bit_fp16
+end arch armv8.2-a+fp16
+
+begin arch armv8-m.base
+ tune for cortex-m23
+ base 8M_BASE
+ isa ARMv8m_base
+end arch armv8-m.base
+
+begin arch armv8-m.main
+ tune for cortex-m7
+ tune flags CO_PROC
+ base 8M_MAIN
+ isa ARMv8m_main
+end arch armv8-m.main
+
+begin arch armv8-m.main+dsp
+ tune for cortex-m33
+ tune flags CO_PROC
+ base 8M_MAIN
+ isa ARMv8m_main bit_ARMv7em
+end arch armv8-m.main+dsp
+
+begin arch iwmmxt
+ tune for iwmmxt
+ tune flags LDSCHED STRONG XSCALE
+ base 5TE
+ isa ARMv5te bit_xscale bit_iwmmxt
+end arch iwmmxt
+
+begin arch iwmmxt2
+ tune for iwmmxt2
+ tune flags LDSCHED STRONG XSCALE
+ base 5TE
+ isa ARMv5te bit_xscale bit_iwmmxt bit_iwmmxt2
+end arch iwmmxt2
+
+# CPU entries
+# format:
+# begin cpu <name>
+#   [cname <c-compatible-name>]
+#   [tune for <cpu-name>]
+#   [tune flags <list>]
+#   architecture <name>
+#   [fpu <name>]
+#   [isa <additional-isa-flags-list>]
+#   [costs <name>]
+# end cpu <name>
+#
+# If omitted, cname is formed from transforming the cpuname to convert
+# non-valid punctuation characters to '_'.
+# If specified, tune for specifies a CPU target to use for tuning this core.
+# isa flags are appended to those defined by the architecture.
+
+
+# V2/V2A Architecture Processors
+begin cpu arm2
+ tune flags CO_PROC NO_MODE32
+ architecture armv2
+ costs slowmul
+end cpu arm2
+
+begin cpu arm250
+ tune flags CO_PROC NO_MODE32
+ architecture armv2
+ costs slowmul
+end cpu arm250
+
+begin cpu arm3
+ tune flags CO_PROC NO_MODE32
+ architecture armv2
+ costs slowmul
+end cpu arm3
+
+
+# V3 Architecture Processors
+begin cpu arm6
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm6
+
+begin cpu arm60
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm60
+
+begin cpu arm600
+ tune flags CO_PROC WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm600
+
+begin cpu arm610
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm610
+
+begin cpu arm620
+ tune flags CO_PROC WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm620
+
+begin cpu arm7
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm7
+
+begin cpu arm7d
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm7d
+
+begin cpu arm7di
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm7di
+
+begin cpu arm70
+ tune flags CO_PROC
+ architecture armv3
+ costs slowmul
+end cpu arm70
+
+begin cpu arm700
+ tune flags CO_PROC WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm700
+
+begin cpu arm700i
+ tune flags CO_PROC WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm700i
+
+begin cpu arm710
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm710
+
+begin cpu arm720
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm720
+
+begin cpu arm710c
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm710c
+
+begin cpu arm7100
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm7100
+
+begin cpu arm7500
+ tune flags WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm7500
+
+# Doesn't have an external co-proc, but does have embedded FPA
+# (the FPA part is no-longer supported).
+begin cpu arm7500fe
+ tune flags CO_PROC WBUF
+ architecture armv3
+ costs slowmul
+end cpu arm7500fe
+
+
+# V3M Architecture Processors
+# arm7m doesn't exist on its own, but only with "D", (and "I"), but
+# those don't alter the code, so arm7m is sometimes used.
+begin cpu arm7m
+ tune flags CO_PROC
+ architecture armv3m
+ costs fastmul
+end cpu arm7m
+
+begin cpu arm7dm
+ tune flags CO_PROC
+ architecture armv3m
+ costs fastmul
+end cpu arm7dm
+
+begin cpu arm7dmi
+ tune flags CO_PROC
+ architecture armv3m
+ costs fastmul
+end cpu arm7dmi
+
+
+# V4 Architecture Processors
+begin cpu arm8
+ tune flags LDSCHED
+ architecture armv4
+ costs fastmul
+end cpu arm8
+
+begin cpu arm810
+ tune flags LDSCHED
+ architecture armv4
+ costs fastmul
+end cpu arm810
+
+begin cpu strongarm
+ tune flags LDSCHED STRONG
+ architecture armv4
+ costs strongarm
+end cpu strongarm
+
+begin cpu strongarm110
+ tune flags LDSCHED STRONG
+ architecture armv4
+ costs strongarm
+end cpu strongarm110
+
+begin cpu strongarm1100
+ tune flags LDSCHED STRONG
+ architecture armv4
+ costs strongarm
+end cpu strongarm1100
+
+begin cpu strongarm1110
+ tune flags LDSCHED STRONG
+ architecture armv4
+ costs strongarm
+end cpu strongarm1110
+
+begin cpu fa526
+ tune flags LDSCHED
+ architecture armv4
+ costs fastmul
+end cpu fa526
+
+begin cpu fa626
+ tune flags LDSCHED
+ architecture armv4
+ costs fastmul
+end cpu fa626
+
+
+# V4T Architecture Processors
+begin cpu arm7tdmi
+ tune flags CO_PROC
+ architecture armv4t
+ costs fastmul
+end cpu arm7tdmi
+
+begin cpu arm7tdmi-s
+ cname arm7tdmis
+ tune flags CO_PROC
+ architecture armv4t
+ costs fastmul
+end cpu arm7tdmi-s
+
+begin cpu arm710t
+ tune flags WBUF
+ architecture armv4t
+ costs fastmul
+end cpu arm710t
+
+begin cpu arm720t
+ tune flags WBUF
+ architecture armv4t
+ costs fastmul
+end cpu arm720t
+
+begin cpu arm740t
+ tune flags WBUF
+ architecture armv4t
+ costs fastmul
+end cpu arm740t
+
+begin cpu arm9
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm9
+
+begin cpu arm9tdmi
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm9tdmi
+
+begin cpu arm920
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm920
+
+begin cpu arm920t
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm920t
+
+begin cpu arm922t
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm922t
+
+begin cpu arm940t
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu arm940t
+
+begin cpu ep9312
+ tune flags LDSCHED
+ architecture armv4t
+ costs fastmul
+end cpu ep9312
+
+
+# V5T Architecture Processors
+begin cpu arm10tdmi
+ tune flags LDSCHED
+ architecture armv5t
+ costs fastmul
+end cpu arm10tdmi
+
+begin cpu arm1020t
+ tune flags LDSCHED
+ architecture armv5t
+ costs fastmul
+end cpu arm1020t
+
+
+# V5TE Architecture Processors
+begin cpu arm9e
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu arm9e
+
+begin cpu arm946e-s
+ cname arm946es
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu arm946e-s
+
+begin cpu arm966e-s
+ cname arm966es
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu arm966e-s
+
+begin cpu arm968e-s
+ cname arm968es
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu arm968e-s
+
+begin cpu arm10e
+ tune flags LDSCHED
+ architecture armv5te
+ costs fastmul
+end cpu arm10e
+
+begin cpu arm1020e
+ tune flags LDSCHED
+ architecture armv5te
+ costs fastmul
+end cpu arm1020e
+
+begin cpu arm1022e
+ tune flags LDSCHED
+ architecture armv5te
+ costs fastmul
+end cpu arm1022e
+
+begin cpu xscale
+ tune flags LDSCHED XSCALE
+ architecture armv5te
+ isa bit_xscale
+ costs xscale
+end cpu xscale
+
+begin cpu iwmmxt
+ tune flags LDSCHED XSCALE
+ architecture iwmmxt
+ costs xscale
+end cpu iwmmxt
+
+begin cpu iwmmxt2
+ tune flags LDSCHED XSCALE
+ architecture iwmmxt2
+ costs xscale
+end cpu iwmmxt2
+
+begin cpu fa606te
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu fa606te
+
+begin cpu fa626te
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu fa626te
+
+begin cpu fmp626
+ tune flags LDSCHED
+ architecture armv5te
+ costs 9e
+end cpu fmp626
+
+begin cpu fa726te
+ tune flags LDSCHED
+ architecture armv5te
+ costs fa726te
+end cpu fa726te
+
+
+# V5TEJ Architecture Processors
+begin cpu arm926ej-s
+ cname arm926ejs
+ tune flags LDSCHED
+ architecture armv5tej
+ costs 9e
+end cpu arm926ej-s
+
+begin cpu arm1026ej-s
+ cname arm1026ejs
+ tune flags LDSCHED
+ architecture armv5tej
+ costs 9e
+end cpu arm1026ej-s
+
+
+# V6 Architecture Processors
+begin cpu arm1136j-s
+ cname arm1136js
+ tune flags LDSCHED
+ architecture armv6j
+ costs 9e
+end cpu arm1136j-s
+
+begin cpu arm1136jf-s
+ cname arm1136jfs
+ tune flags LDSCHED
+ architecture armv6j
+ fpu vfpv2
+ costs 9e
+end cpu arm1136jf-s
+
+begin cpu arm1176jz-s
+ cname arm1176jzs
+ tune flags LDSCHED
+ architecture armv6kz
+ costs 9e
+end cpu arm1176jz-s
+
+begin cpu arm1176jzf-s
+ cname arm1176jzfs
+ tune flags LDSCHED
+ architecture armv6kz
+ fpu vfpv2
+ costs 9e
+end cpu arm1176jzf-s
+
+begin cpu mpcorenovfp
+ tune flags LDSCHED
+ architecture armv6k
+ costs 9e
+end cpu mpcorenovfp
+
+begin cpu mpcore
+ tune flags LDSCHED
+ architecture armv6k
+ fpu vfpv2
+ costs 9e
+end cpu mpcore
+
+begin cpu arm1156t2-s
+ cname arm1156t2s
+ tune flags LDSCHED
+ architecture armv6t2
+ costs v6t2
+end cpu arm1156t2-s
+
+begin cpu arm1156t2f-s
+ cname arm1156t2fs
+ tune flags LDSCHED
+ architecture armv6t2
+ fpu vfpv2
+ costs v6t2
+end cpu arm1156t2f-s
+
+
+# V6M Architecture Processors
+begin cpu cortex-m1
+ cname cortexm1
+ tune flags LDSCHED
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m1
+
+begin cpu cortex-m0
+ cname cortexm0
+ tune flags LDSCHED
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m0
+
+begin cpu cortex-m0plus
+ cname cortexm0plus
+ tune flags LDSCHED
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m0plus
+
+
+# V6M Architecture Processors for small-multiply implementations.
+begin cpu cortex-m1.small-multiply
+ cname cortexm1smallmultiply
+ tune for cortex-m1
+ tune flags LDSCHED SMALLMUL
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m1.small-multiply
+
+begin cpu cortex-m0.small-multiply
+ cname cortexm0smallmultiply
+ tune for cortex-m0
+ tune flags LDSCHED SMALLMUL
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m0.small-multiply
+
+begin cpu cortex-m0plus.small-multiply
+ cname cortexm0plussmallmultiply
+ tune for cortexm0-plus
+ tune flags LDSCHED SMALLMUL
+ architecture armv6-m
+ costs v6m
+end cpu cortex-m0plus.small-multiply
+
+
+# V7 Architecture Processors
+begin cpu generic-armv7-a
+ cname genericv7a
+ tune flags LDSCHED
+ architecture armv7-a
+ costs cortex
+end cpu generic-armv7-a
+
+begin cpu cortex-a5
+ cname cortexa5
+ tune flags LDSCHED
+ architecture armv7-a
+ costs cortex_a5
+end cpu cortex-a5
+
+begin cpu cortex-a7
+ cname cortexa7
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a7
+end cpu cortex-a7
+
+begin cpu cortex-a8
+ cname cortexa8
+ tune flags LDSCHED
+ architecture armv7-a
+ costs cortex_a8
+end cpu cortex-a8
+
+begin cpu cortex-a9
+ cname cortexa9
+ tune flags LDSCHED
+ architecture armv7-a
+ costs cortex_a9
+end cpu cortex-a9
+
+begin cpu cortex-a12
+ cname cortexa12
+ tune for cortex-a17
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a12
+end cpu cortex-a12
+
+begin cpu cortex-a15
+ cname cortexa15
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a15
+end cpu cortex-a15
+
+begin cpu cortex-a17
+ cname cortexa17
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a12
+end cpu cortex-a17
+
+begin cpu cortex-r4
+ cname cortexr4
+ tune flags LDSCHED
+ architecture armv7-r
+ costs cortex
+end cpu cortex-r4
+
+begin cpu cortex-r4f
+ cname cortexr4f
+ tune flags LDSCHED
+ architecture armv7-r
+ costs cortex
+end cpu cortex-r4f
+
+begin cpu cortex-r5
+ cname cortexr5
+ tune flags LDSCHED
+ architecture armv7-r
+ isa bit_adiv
+ costs cortex
+end cpu cortex-r5
+
+begin cpu cortex-r7
+ cname cortexr7
+ tune flags LDSCHED
+ architecture armv7-r
+ isa bit_adiv
+ costs cortex
+end cpu cortex-r7
+
+begin cpu cortex-r8
+ cname cortexr8
+ tune for cortex-r7
+ tune flags LDSCHED
+ architecture armv7-r
+ isa bit_adiv
+ costs cortex
+end cpu cortex-r8
+
+begin cpu cortex-m7
+ cname cortexm7
+ tune flags LDSCHED
+ architecture armv7e-m
+ isa quirk_no_volatile_ce
+ costs cortex_m7
+end cpu cortex-m7
+
+begin cpu cortex-m4
+ cname cortexm4
+ tune flags LDSCHED
+ architecture armv7e-m
+ costs v7m
+end cpu cortex-m4
+
+begin cpu cortex-m3
+ cname cortexm3
+ tune flags LDSCHED
+ architecture armv7-m
+ isa quirk_cm3_ldrd
+ costs v7m
+end cpu cortex-m3
+
+begin cpu marvell-pj4
+ tune flags LDSCHED
+ architecture armv7-a
+ costs marvell_pj4
+end cpu marvell-pj4
+
+
+# V7 big.LITTLE implementations
+begin cpu cortex-a15.cortex-a7
+ cname cortexa15cortexa7
+ tune for cortex-a7
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a15
+end cpu cortex-a15.cortex-a7
+
+begin cpu cortex-a17.cortex-a7
+ cname cortexa17cortexa7
+ tune for cortex-a7
+ tune flags LDSCHED
+ architecture armv7ve
+ costs cortex_a12
+end cpu cortex-a17.cortex-a7
+
+
+# V8 A-profile Architecture Processors
+begin cpu cortex-a32
+ cname cortexa32
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a35
+end cpu cortex-a32
+
+begin cpu cortex-a35
+ cname cortexa35
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a35
+end cpu cortex-a35
+
+begin cpu cortex-a53
+ cname cortexa53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a53
+end cpu cortex-a53
+
+begin cpu cortex-a57
+ cname cortexa57
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a57
+end cpu cortex-a57
+
+begin cpu cortex-a72
+ cname cortexa72
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a57
+end cpu cortex-a72
+
+begin cpu cortex-a73
+ cname cortexa73
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a73
+end cpu cortex-a73
+
+begin cpu exynos-m1
+ cname exynosm1
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs exynosm1
+end cpu exynos-m1
+
+begin cpu falkor
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs qdf24xx
+end cpu falkor
+
+begin cpu qdf24xx
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs qdf24xx
+end cpu qdf24xx
+
+begin cpu xgene1
+ tune flags LDSCHED
+ architecture armv8-a
+ costs xgene1
+end cpu xgene1
+
+
+# V8 A-profile big.LITTLE implementations
+begin cpu cortex-a57.cortex-a53
+ cname cortexa57cortexa53
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a57
+end cpu cortex-a57.cortex-a53
+
+begin cpu cortex-a72.cortex-a53
+ cname cortexa72cortexa53
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a57
+end cpu cortex-a72.cortex-a53
+
+begin cpu cortex-a73.cortex-a35
+ cname cortexa73cortexa35
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a73
+end cpu cortex-a73.cortex-a35
+
+begin cpu cortex-a73.cortex-a53
+ cname cortexa73cortexa53
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8-a+crc
+ costs cortex_a73
+end cpu cortex-a73.cortex-a53
+
+
+# V8 M-profile implementations.
+begin cpu cortex-m23
+ cname cortexm23
+ tune flags LDSCHED
+ architecture armv8-m.base
+ costs v6m
+end cpu cortex-m23
+
+begin cpu cortex-m33
+ cname cortexm33
+ tune flags LDSCHED
+ architecture armv8-m.main+dsp
+ costs v7m
+end cpu cortex-m33
+
+# FPU entries
+# format:
+# begin fpu <name>
+#   isa <isa-flags-list>
+# end fpu <name>
+
+begin fpu vfp
+ isa VFPv2 FP_DBL
+end fpu vfp
+
+begin fpu vfpv2
+ isa VFPv2 FP_DBL
+end fpu vfpv2
+
+begin fpu vfpv3
+ isa VFPv3 FP_D32
+end fpu vfpv3
+
+begin fpu vfpv3-fp16
+ isa VFPv3 FP_D32 bit_fp16conv
+end fpu vfpv3-fp16
+
+begin fpu vfpv3-d16
+ isa VFPv3 FP_DBL
+end fpu vfpv3-d16
+
+begin fpu vfpv3-d16-fp16
+ isa VFPv3 FP_DBL bit_fp16conv
+end fpu vfpv3-d16-fp16
+
+begin fpu vfpv3xd
+ isa VFPv3
+end fpu vfpv3xd
+
+begin fpu vfpv3xd-fp16
+ isa VFPv3 bit_fp16conv
+end fpu vfpv3xd-fp16
+
+begin fpu neon
+ isa VFPv3 NEON
+end fpu neon
+
+begin fpu neon-vfpv3
+ isa VFPv3 NEON
+end fpu neon-vfpv3
+
+begin fpu neon-fp16
+ isa VFPv3 NEON bit_fp16conv
+end fpu neon-fp16
+
+begin fpu vfpv4
+ isa VFPv4 FP_D32
+end fpu vfpv4
+
+begin fpu neon-vfpv4
+ isa VFPv4 NEON
+end fpu neon-vfpv4
+
+begin fpu vfpv4-d16
+ isa VFPv4 FP_DBL
+end fpu vfpv4-d16
+
+begin fpu fpv4-sp-d16
+ isa VFPv4
+end fpu fpv4-sp-d16
+
+begin fpu fpv5-sp-d16
+ isa FPv5
+end fpu fpv5-sp-d16
+
+begin fpu fpv5-d16
+ isa FPv5 FP_DBL
+end fpu fpv5-d16
+
+begin fpu fp-armv8
+ isa FP_ARMv8 FP_D32
+end fpu fp-armv8
+
+begin fpu neon-fp-armv8
+ isa FP_ARMv8 NEON
+end fpu neon-fp-armv8
+
+begin fpu crypto-neon-fp-armv8
+ isa FP_ARMv8 CRYPTO
+end fpu crypto-neon-fp-armv8
+
+# Compatibility aliases.
+begin fpu vfp3
+ isa VFPv3 FP_D32
+end fpu vfp3
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
deleted file mode 100644
index 24f61c3..0000000
--- a/gcc/config/arm/arm-fpus.def
+++ /dev/null
@@ -1,51 +0,0 @@
-/* ARM FPU variants.
-   Copyright (C) 1991-2017 Free Software Foundation, Inc.
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-/* Before using #include to read this file, define a macro:
-
-      ARM_FPU(NAME, CNAME, ISA)
-
-   NAME is the publicly visible option name.
-   CNAME is a C-compatible variable name substring.
-   ISA is the list of feature bits that this FPU provides.
-
-   genopt.sh assumes no whitespace up to the first "," in each entry.  */
-
-ARM_FPU("vfp",			vfp,		      ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv2",		vfpv2,		      ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv3",		vfpv3,		      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("vfpv3-fp16",		vfpv3_fp16,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv3-d16",		vfpv3_d16,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv3-d16-fp16",	vfpv3_d16_fp16,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv3xd",		vfpv3xd,	      ISA_FEAT(ISA_VFPv3))
-ARM_FPU("vfpv3xd-fp16",		vfpv3xd_fp16,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("neon",			neon,		      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
-ARM_FPU("neon-vfpv3",		neon_vfpv3,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
-ARM_FPU("neon-fp16",		neon_fp16,	      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv4",		vfpv4,		      ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("neon-vfpv4",		neon_vfpv4,	      ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
-ARM_FPU("vfpv4-d16",		vfpv4_d16,	      ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("fpv4-sp-d16",		fpv4_sp_d16,	      ISA_FEAT(ISA_VFPv4))
-ARM_FPU("fpv5-sp-d16",		fpv5_sp_d16,	      ISA_FEAT(ISA_FPv5))
-ARM_FPU("fpv5-d16",		fpv5_d16,	      ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("fp-armv8",		fp_armv8,	      ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("neon-fp-armv8",	neon_fp_armv8,	      ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
-ARM_FPU("crypto-neon-fp-armv8", crypto_neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
-/* Compatibility aliases.  */
-ARM_FPU("vfp3",			vfp3,		      ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index ab2a66a..822958d 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -27,28 +27,7 @@
 
 #include "arm-flags.h"
 #include "arm-isa.h"
-
-/* The various ARM cores.  */
-enum processor_type
-{
-#undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
-  TARGET_CPU_##INTERNAL_IDENT,
-#include "arm-cores.def"
-#undef ARM_CORE
-  /* Used to indicate that no processor has been specified.  */
-  TARGET_CPU_arm_none
-};
-
-/* The various ARM FPUs.  */
-enum fpu_type
-{
-#undef ARM_FPU
-#define ARM_FPU(NAME, CNAME, ISA) TARGET_FPU_##CNAME,
-#include "arm-fpus.def"
-  TARGET_FPU_auto
-#undef ARM_FPU
-};
+#include "arm-cpu.h"
 
 /* Which __fp16 format to use.
    The enumeration values correspond to the numbering for the
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index cfd46e0..cbcd85d 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -1,23 +1,23 @@
 ; -*- buffer-read-only: t -*-
-; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def
-; and arm-fpus.def.
+; Generated automatically by parsecpu.awk from arm-cpus.in.
+; Do not edit.
 
 ; Copyright (C) 2011-2017 Free Software Foundation, Inc.
-;
+
 ; This file is part of GCC.
-;
-; GCC is free software; you can redistribute it and/or modify it under
-; the terms of the GNU General Public License as published by the Free
-; Software Foundation; either version 3, or (at your option) any later
-; version.
-;
-; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or
-; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-; for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING3.  If not see
+
+; GCC is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as
+; published by the Free Software Foundation; either version 3,
+; or (at your option) any later version.
+
+; GCC is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+
+; You should have received a copy of the GNU General Public
+; License along with GCC; see the file COPYING3.  If not see
 ; <http://www.gnu.org/licenses/>.
 
 Enum
@@ -389,79 +389,82 @@ EnumValue
 Enum(arm_arch) String(armv5te) Value(9)
 
 EnumValue
-Enum(arm_arch) String(armv6) Value(10)
+Enum(arm_arch) String(armv5tej) Value(10)
+
+EnumValue
+Enum(arm_arch) String(armv6) Value(11)
 
 EnumValue
-Enum(arm_arch) String(armv6j) Value(11)
+Enum(arm_arch) String(armv6j) Value(12)
 
 EnumValue
-Enum(arm_arch) String(armv6k) Value(12)
+Enum(arm_arch) String(armv6k) Value(13)
 
 EnumValue
-Enum(arm_arch) String(armv6z) Value(13)
+Enum(arm_arch) String(armv6z) Value(14)
 
 EnumValue
-Enum(arm_arch) String(armv6kz) Value(14)
+Enum(arm_arch) String(armv6kz) Value(15)
 
 EnumValue
-Enum(arm_arch) String(armv6zk) Value(15)
+Enum(arm_arch) String(armv6zk) Value(16)
 
 EnumValue
-Enum(arm_arch) String(armv6t2) Value(16)
+Enum(arm_arch) String(armv6t2) Value(17)
 
 EnumValue
-Enum(arm_arch) String(armv6-m) Value(17)
+Enum(arm_arch) String(armv6-m) Value(18)
 
 EnumValue
-Enum(arm_arch) String(armv6s-m) Value(18)
+Enum(arm_arch) String(armv6s-m) Value(19)
 
 EnumValue
-Enum(arm_arch) String(armv7) Value(19)
+Enum(arm_arch) String(armv7) Value(20)
 
 EnumValue
-Enum(arm_arch) String(armv7-a) Value(20)
+Enum(arm_arch) String(armv7-a) Value(21)
 
 EnumValue
-Enum(arm_arch) String(armv7ve) Value(21)
+Enum(arm_arch) String(armv7ve) Value(22)
 
 EnumValue
-Enum(arm_arch) String(armv7-r) Value(22)
+Enum(arm_arch) String(armv7-r) Value(23)
 
 EnumValue
-Enum(arm_arch) String(armv7-m) Value(23)
+Enum(arm_arch) String(armv7-m) Value(24)
 
 EnumValue
-Enum(arm_arch) String(armv7e-m) Value(24)
+Enum(arm_arch) String(armv7e-m) Value(25)
 
 EnumValue
-Enum(arm_arch) String(armv8-a) Value(25)
+Enum(arm_arch) String(armv8-a) Value(26)
 
 EnumValue
-Enum(arm_arch) String(armv8-a+crc) Value(26)
+Enum(arm_arch) String(armv8-a+crc) Value(27)
 
 EnumValue
-Enum(arm_arch) String(armv8.1-a) Value(27)
+Enum(arm_arch) String(armv8.1-a) Value(28)
 
 EnumValue
-Enum(arm_arch) String(armv8.2-a) Value(28)
+Enum(arm_arch) String(armv8.2-a) Value(29)
 
 EnumValue
-Enum(arm_arch) String(armv8.2-a+fp16) Value(29)
+Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.base) Value(30)
+Enum(arm_arch) String(armv8-m.base) Value(31)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.main) Value(31)
+Enum(arm_arch) String(armv8-m.main) Value(32)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.main+dsp) Value(32)
+Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(33)
+Enum(arm_arch) String(iwmmxt) Value(34)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(34)
+Enum(arm_arch) String(iwmmxt2) Value(35)
 
 Enum
 Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 22e4a53..13db413 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -1,5 +1,25 @@
-;; -*- buffer-read-only: t -*-
-;; Generated automatically by gentune.sh from arm-cores.def
+; -*- buffer-read-only: t -*-
+; Generated automatically by parsecpu.awk from arm-cpus.in.
+; Do not edit.
+
+; Copyright (C) 2011-2017 Free Software Foundation, Inc.
+
+; This file is part of GCC.
+
+; GCC is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as
+; published by the Free Software Foundation; either version 3,
+; or (at your option) any later version.
+
+; GCC is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+
+; You should have received a copy of the GNU General Public
+; License along with GCC; see the file COPYING3.  If not see
+; <http://www.gnu.org/licenses/>.
+
 (define_attr "tune"
 	"arm2,arm250,arm3,
 	arm6,arm60,arm600,
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index ccdf1ab..1fbeb56 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2293,33 +2293,8 @@ const struct tune_params arm_fa726te_tune =
   tune_params::SCHED_AUTOPREF_OFF
 };
 
-
-/* Not all of these give usefully different compilation alternatives,
-   but there is no simple way of generalizing them.  */
-static const struct processors all_cores[] =
-{
-  /* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)	\
-  {NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
-   {ISA isa_nobit}, &arm_##COSTS##_tune},
-#include "arm-cores.def"
-#undef ARM_CORE
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
-};
-
-static const struct processors all_architectures[] =
-{
-  /* ARM Architectures */
-  /* We don't specify tuning costs here as it will be figured out
-     from the core.  */
-
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)			\
-  {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH,	\
-  {ISA isa_nobit}, NULL},
-#include "arm-arches.def"
-#undef ARM_ARCH
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
-};
+/* Auto-generated CPU, FPU and architecture tables.  */
+#include "arm-cpu-data.h"
 
 /* The name of the preprocessor macro to define for this architecture.  PROFILE
    is replaced by the architecture name (eg. 8A) in arm_option_override () and
@@ -2327,17 +2302,6 @@ static const struct processors all_architectures[] =
 
 char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
 
-/* Available values for -mfpu=.  */
-
-const struct arm_fpu_desc all_fpus[] =
-{
-#undef ARM_FPU
-#define ARM_FPU(NAME, CNAME, ISA)	\
-  { NAME, {ISA isa_nobit} },
-#include "arm-fpus.def"
-#undef ARM_FPU
-};
-
 /* Supported TLS relocations.  */
 
 enum tls_reloc {
diff --git a/gcc/config/arm/genopt.sh b/gcc/config/arm/genopt.sh
deleted file mode 100755
index 5565018..0000000
--- a/gcc/config/arm/genopt.sh
+++ /dev/null
@@ -1,98 +0,0 @@
-#!/bin/sh
-# Generate arm-tables.opt from the lists in *.def.
-# Copyright (C) 2011-2017 Free Software Foundation, Inc.
-#
-# This file is part of GCC.
-#
-# GCC is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GCC is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3.  If not see
-# <http://www.gnu.org/licenses/>.
-
-cat <<EOF
-; -*- buffer-read-only: t -*-
-; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def
-; and arm-fpus.def.
-
-; Copyright (C) 2011-2017 Free Software Foundation, Inc.
-;
-; This file is part of GCC.
-;
-; GCC is free software; you can redistribute it and/or modify it under
-; the terms of the GNU General Public License as published by the Free
-; Software Foundation; either version 3, or (at your option) any later
-; version.
-;
-; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or
-; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-; for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING3.  If not see
-; <http://www.gnu.org/licenses/>.
-
-Enum
-Name(processor_type) Type(enum processor_type)
-Known ARM CPUs (for use with the -mcpu= and -mtune= options):
-
-EOF
-
-awk -F'[(, 	]+' '/^ARM_CORE/ {
-    name = $2
-    enum = $3
-    gsub("\"", "", name)
-    print "EnumValue"
-    print "Enum(processor_type) String(" name ") Value( TARGET_CPU_" enum ")"
-    print ""
-}' $1/arm-cores.def
-
-cat <<EOF
-Enum
-Name(arm_arch) Type(int)
-Known ARM architectures (for use with the -march= option):
-
-EOF
-
-awk -F'[(, 	]+' 'BEGIN {
-    value = 0
-}
-/^ARM_ARCH/ {
-    name = $2
-    gsub("\"", "", name)
-    print "EnumValue"
-    print "Enum(arm_arch) String(" name ") Value(" value ")"
-    print ""
-    value++
-}' $1/arm-arches.def
-
-cat <<EOF
-Enum
-Name(arm_fpu) Type(enum fpu_type)
-Known ARM FPUs (for use with the -mfpu= option):
-
-EOF
-
-awk -F'[(, 	]+' '
-/^ARM_FPU/ {
-    name = $2
-    enum = $3
-    gsub("\"", "", name)
-    print "EnumValue"
-    print "Enum(arm_fpu) String(" name ") Value(TARGET_FPU_" enum ")"
-    print ""
-}
-END {
-    print "EnumValue"
-    print "Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)"
-}' $1/arm-fpus.def
-
diff --git a/gcc/config/arm/gentune.sh b/gcc/config/arm/gentune.sh
deleted file mode 100755
index 16a094f..0000000
--- a/gcc/config/arm/gentune.sh
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/bin/sh
-# Generate arm-tune.md, a file containing the tune attribute from the list of 
-# CPUs in arm-cores.def
-# Copyright (C) 2004-2017 Free Software Foundation, Inc.
-#
-# This file is part of GCC.
-#
-# GCC is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GCC is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3.  If not see
-# <http://www.gnu.org/licenses/>.
-
-echo ";; -*- buffer-read-only: t -*-"
-echo ";; Generated automatically by gentune.sh from arm-cores.def"
-
-allcores=`awk -F'[(, 	]+' '/^ARM_CORE/ { cores = cores$3"," } END { print cores } ' $1`
-
-echo "(define_attr \"tune\""
-echo "	\"$allcores\"" | sed -e 's/,"$/"/' | sed -e 's/\([a-z0-9_]\+,[a-z0-9_]\+,[a-z0-9_]\+,\)/\1\n\t/g'
-echo "	(const (symbol_ref \"((enum attr_tune) arm_tune)\")))"
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
new file mode 100644
index 0000000..c7f3e12
--- /dev/null
+++ b/gcc/config/arm/parsecpu.awk
@@ -0,0 +1,491 @@
+# Manipulate the CPU, FPU and architecture descriptions for ARM.
+# Copyright (C) 2017 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Invoke this with '-v cmd=<cmd>"
+# where <cmd> is one of:
+#	data: Print the standard 'C' data tables for the CPUs
+#	common-data: Print the 'C' data for shared driver/compiler files
+#	headers: Print the standard 'C' headers for the CPUs
+#	md: Print the machine description fragment
+#	opt: Print the option tables fragment
+#	chkcpu <name>: Checks that <name> is a valid CPU
+#	chktune <name>: Checks that <name> is a valid CPU
+#	chkfpu <name>: Checks that <name> is a valid FPU
+#	chkarch <name>: Checks that <arch> is a valid architecture
+
+function fatal (m) {
+    print "error ("lineno"): " m > "/dev/stderr"
+    exit 1
+}
+
+function toplevel () {
+    if (cpu_name != "") fatal("missing \"end cpu\"")
+    if (arch_name != "") fatal("missing \"end arch\"")
+    if (fpu_name != "") fatal("missing \"end fpu\"")
+}
+
+function boilerplate (style) {
+    ce = ""
+    if (style == "C" ) {
+	cs = "/* "
+	cc = "   "
+	ce = "  */"
+    } else if (style == "md") {
+	cc = "; "
+	cs = cc
+    } else if (style == "sh") {
+	cc = "# "
+	cs = cc
+    } else fatal("Unknown comment style: "style)
+
+    print cs "-*- buffer-read-only: t -*-"
+
+    print cc "Generated automatically by parsecpu.awk from arm-cpus.in."
+    print cc "Do not edit."
+    print ""
+    print cc "Copyright (C) 2011-2017 Free Software Foundation, Inc."
+    print ""
+    print cc "This file is part of GCC."
+    print ""
+    print cc "GCC is free software; you can redistribute it and/or modify"
+    print cc "it under the terms of the GNU General Public License as"
+    print cc "published by the Free Software Foundation; either version 3,"
+    print cc "or (at your option) any later version."
+    print ""
+    print cc "GCC is distributed in the hope that it will be useful,"
+    print cc "but WITHOUT ANY WARRANTY; without even the implied warranty of"
+    print cc "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the"
+    print cc "GNU General Public License for more details."
+    print ""
+    print cc "You should have received a copy of the GNU General Public"
+    print cc "License along with GCC; see the file COPYING3.  If not see"
+    print cc "<http://www.gnu.org/licenses/>." ce
+    print ""
+}
+
+function tune_flag_pfx (f) {
+    return "TF_" f
+}
+
+function isa_pfx (f) {
+    if (f ~ /^(bit|quirk)_.*/) return "isa_" f
+    return "ISA_" f
+}
+
+function gen_headers () {
+    boilerplate("C")
+
+    print "enum processor_type"
+    print "{"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  TARGET_CPU_"cpu_cnames[cpus[n]]","
+    }
+    print "  TARGET_CPU_arm_none"
+    print "};\n"
+
+    print "enum fpu_type"
+    print "{"
+
+    nfpus = split (fpu_list, fpus)
+
+    for (n = 1; n <= nfpus; n++) {
+	print "  TARGET_FPU_"fpu_cnames[fpus[n]]","
+    }
+    print "  TARGET_FPU_auto"
+    print "};"
+}
+
+function gen_data () {
+    boilerplate("C")
+
+    print "static const struct processors all_cores[] ="
+    print "{"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  {"
+	print "    \"" cpus[n] "\", TARGET_CPU_" cpu_cnames[cpus[n]] ","
+	if (cpus[n] in cpu_tune_flags) {
+	    print "    (" cpu_tune_flags[cpus[n]] "),"
+	} else print "    0,"
+	if (! (cpu_arch[cpus[n]] in arch_isa)) {
+	    fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n])
+	}
+	print "    \"" arch_base[cpu_arch[cpus[n]]] "\", BASE_ARCH_" \
+	    arch_base[cpu_arch[cpus[n]]] ","
+	print "    {"
+	print "      " arch_isa[cpu_arch[cpus[n]]] ","
+	if (cpus[n] in cpu_fpu) print "      " fpu_isa[cpu_fpu[cpus[n]]] ","
+	if (cpus[n] in cpu_isa) print "      " cpu_isa[cpus[n]] ","
+	print "      isa_nobit"
+	print "    },"
+	print "    &arm_" cpu_cost[cpus[n]] "_tune"
+	print "  },"
+    }
+
+    print "  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
+	" {isa_nobit}, NULL}"
+    print "};\n"
+
+    print "static const struct processors all_architectures[] ="
+    print "{"
+
+    narchs = split (arch_list, archs)
+
+    for (n = 1; n <= narchs; n++) {
+	print "  {"
+	if (! (arch_tune_for[archs[n]] in cpu_cnames)) {
+	    fatal("unknown \"tune for\" target " arch_tune_for[archs[n]] \
+		  "for architecture " archs[n])
+	}
+	print "    \"" archs[n] \
+	    "\", TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] ","
+	if (archs[n] in arch_tune_flags) {
+	    print "    (" arch_tune_flags[archs[n]] "),"
+	} else print "    0,"
+	print "    \"" arch_base[archs[n]] "\", BASE_ARCH_" \
+	    arch_base[archs[n]] ","
+	print "    {"
+	print "      " arch_isa[archs[n]] ","
+	print "      isa_nobit"
+	print "    },"
+	print "    NULL"
+	print "  },"
+    }
+
+    print "  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
+	" {isa_nobit}, NULL}"
+    print "};\n"
+
+    print "const struct arm_fpu_desc all_fpus[] ="
+    print "{"
+
+    nfpus = split (fpu_list, fpus)
+
+    for (n = 1; n <= nfpus; n++) {
+	print "  {"
+	print "    \"" fpus[n] "\","
+	print "    {"
+	print "      " fpu_isa[fpus[n]] ","
+	print "      isa_nobit"
+	print "    }"
+	print "  },"
+    }
+
+    print "};"
+}
+
+function gen_comm_data () {
+    boilerplate("C")
+
+    print "static const struct arm_arch_core_flag arm_arch_core_flags[] ="
+    print "{"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  {"
+	print "    \"" cpus[n] "\","
+	if (! (cpu_arch[cpus[n]] in arch_isa)) {
+	    fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n])
+	}
+	print "    {"
+	print "      " arch_isa[cpu_arch[cpus[n]]] ","
+	if (cpus[n] in cpu_fpu)	print "      " fpu_isa[cpu_fpu[cpus[n]]] ","
+	if (cpus[n] in cpu_isa)	print "      " cpu_isa[cpus[n]] ","
+	print "      isa_nobit"
+	print "    },"
+	print "  },"
+    }
+
+    narchs = split (arch_list, archs)
+
+    for (n = 1; n <= narchs; n++) {
+	print "  {"
+	print "    \"" archs[n] "\","
+	print "    {"
+	print "      " arch_isa[archs[n]] ","
+	print "      isa_nobit"
+	print "    },"
+	print "  },"
+    }
+
+    print "};\n"
+}
+
+function gen_md () {
+    boilerplate("md")
+
+    z = ORS
+    ORS = ""
+    print "(define_attr \"tune\"\n\t\""
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n < ncpus; n++) {
+	if ((n % 3) != 0) {
+	    ORS = ","
+	} else ORS = ",\n\t"
+	print cpu_cnames[cpus[n]]
+    }
+    ORS = z
+    print cpu_cnames[cpus[ncpus]]"\""
+    print "\t(const (symbol_ref \"((enum attr_tune) arm_tune)\")))"
+}
+
+function gen_opt () {
+    boilerplate("md")
+
+    print "Enum"
+    print "Name(processor_type) Type(enum processor_type)"
+    print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "EnumValue"
+	print "Enum(processor_type) String(" cpus[n] \
+	    ") Value( TARGET_CPU_"cpu_cnames[cpus[n]]")"
+	print ""
+    }
+
+    print "Enum"
+    print "Name(arm_arch) Type(int)"
+    print "Known ARM architectures (for use with the -march= option):\n"
+
+    narchs = split (arch_list, archs)
+
+    for (n = 1; n <= narchs; n++) {
+	print "EnumValue"
+	print "Enum(arm_arch) String(" archs[n] \
+	    ") Value("n - 1")"
+	print ""
+    }
+
+    print "Enum"
+    print "Name(arm_fpu) Type(enum fpu_type)"
+    print "Known ARM FPUs (for use with the -mfpu= option):\n"
+
+    nfpus = split (fpu_list, fpus)
+
+    for (n = 1; n <= nfpus; n++) {
+	print "EnumValue"
+	print "Enum(arm_fpu) String(" fpus[n] \
+	    ") Value(TARGET_FPU_"fpu_cnames[fpus[n]]")"
+	print ""
+    }
+
+    print "EnumValue"
+    print "Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)"
+}
+
+function check_cpu (name) {
+    if (name in cpu_cnames) {
+	print cpu_cnames[name]
+    } else print "error"
+}
+
+function check_fpu (name) {
+    if (name in fpu_cnames) {
+	print fpu_cnames[name]
+    } else print "error"
+}
+
+function check_arch (name) {
+    if (name in arch_isa) {
+	print name
+    } else print "error"
+}
+
+BEGIN {
+    cpu_name = ""
+    arch_name = ""
+    fpu_name = ""
+    lineno = 0
+    if (cmd == "") fatal("Usage parsecpu.awk -v cmd=<xyz>")
+}
+
+// {
+    lineno++
+    parse_ok = 0
+}
+
+/^#/ {
+    parse_ok = 1
+}
+
+/^begin fpu / {
+    toplevel()
+    fpu_name = $3
+    parse_ok = 1
+}
+
+/^end fpu / {
+    if (fpu_name != $3) fatal("mimatched end fpu")
+    if (! (fpu_name in fpu_isa)) {
+	fatal("fpu definition \"" fpu_name "\" lacks an \"isa\" statement")
+    }
+    fpu_cnames[fpu_name] = fpu_name
+    gsub(/[-+.]/, "_", fpu_cnames[fpu_name])
+    fpu_list = fpu_list " " fpu_name
+    fpu_name = ""
+    parse_ok = 1
+}
+
+/^begin arch / {
+    toplevel()
+    arch_name = $3
+    parse_ok = 1
+}
+
+/^[ 	]*base / {
+    if (arch_name == "") fatal("\"base\" statement outside of arch block")
+    arch_base[arch_name] = $2
+    parse_ok = 1
+}
+
+/^end arch / {
+    if (arch_name != $3) fatal("mimatched end arch")
+    if (! arch_name in arch_tune_for) {
+	fatal("arch definition lacks a \"tune for\" statement")
+    }
+    if (! arch_name in arch_isa) {
+	fatal("arch definition lacks an \"isa\" statement")
+    }
+    arch_list = arch_list " " arch_name
+    arch_name = ""
+    parse_ok = 1
+}
+
+/^begin cpu / {
+    toplevel()
+    cpu_name = $3
+    parse_ok = 1
+}
+
+/^[ 	]*cname / {
+    if (cpu_name == "") fatal("\"cname\" outside of cpu block")
+    cpu_cnames[cpu_name] = $2
+    parse_ok = 1
+}
+
+/^[ 	]*tune for / {
+    if (cpu_name != "") {
+	cpu_tune_for[cpu_name] = $3
+    } else if (arch_name != "") {
+	arch_tune_for[arch_name] = $3
+    } else fatal("\"tune for\" outside of cpu or arch block")
+    parse_ok = 1
+}
+
+/^[ 	]*tune flags / {
+    flags=""
+    flag_count = NF
+    for (n = 3; n <= flag_count; n++) {
+	if (n == 3) {
+	    flags = tune_flag_pfx($n)
+	} else flags = flags " | " tune_flag_pfx($n)
+    }
+    if (cpu_name != "") {
+	cpu_tune_flags[cpu_name] = flags
+    } else if (arch_name != "") {
+	arch_tune_flags[arch_name] = flags
+    } else fatal("\"tune flags\" outside of cpu or arch block")
+    parse_ok = 1
+}
+
+/^[ 	]*architecture / {
+    if (cpu_name == "") fatal("\"architecture\" outside of cpu block")
+    cpu_arch[cpu_name] = $2
+    parse_ok = 1
+}
+
+/^[ 	]*fpu / {
+    if (cpu_name == "") fatal("\"fpu\" outside of cpu block")
+    cpu_fpu[cpu_name] = $2
+    parse_ok = 1
+}
+
+/^[ 	]*isa / {
+    flags=""
+    flag_count = NF
+    for (n = 2; n <= flag_count; n++) {
+	if (n == 2) {
+	    flags = isa_pfx($n)
+	} else flags = flags "," isa_pfx($n)
+    }
+    if (cpu_name != "") {
+	cpu_isa[cpu_name] = flags
+    } else if (arch_name != "") {
+	arch_isa[arch_name] = flags
+    } else  if (fpu_name != "") {
+	fpu_isa[fpu_name] = flags
+    } else fatal("\"isa\" outside of cpu, fpu or arch block")
+    parse_ok = 1
+}
+
+/^[ 	]*costs / {
+    if (cpu_name == "") fatal("\"costs\" outside of cpu block")
+    cpu_cost[cpu_name] = $2
+    parse_ok = 1
+}
+
+/^end cpu / {
+    if (cpu_name != $3) fatal("mimatched end cpu")
+    if (! (cpu_name in cpu_cnames)) {
+	cpu_cnames[cpu_name] = cpu_name
+	gsub(/[-+.]/, "_", cpu_cnames[cpu_name])
+    }
+    if (! cpu_name in cpu_arch) fatal("cpu definition lacks an architecture")
+    cpu_list = cpu_list " " cpu_name
+    cpu_name = ""
+    parse_ok = 1
+}
+
+/[^\s]/ {
+    if (! parse_ok) fatal("Unrecognized statement: " $0)
+}
+
+END {
+    toplevel()
+    if (cmd == "data") {
+	gen_data()
+    } else if (cmd == "common-data") {
+	gen_comm_data()
+    } else if (cmd == "headers") {
+	gen_headers()
+    } else if (cmd == "md") {
+	gen_md()
+    } else if (cmd == "opt") {
+	gen_opt()
+    } else if (cmd ~ /^chk(cpu|tune) /) {
+	split (cmd, target)
+	check_cpu(target[2])
+    } else if (cmd ~ /^chkarch /) {
+	split (cmd, target)
+	check_arch(target[2])
+    } else if (cmd ~ /^chkfpu /) {
+	split (cmd, target)
+	check_fpu(target[2])
+    } else fatal("unrecognized command: "cmd)
+}
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index a29fa7f..b6a3cb4 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -18,8 +18,7 @@
 # along with GCC; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
 
-TM_H += $(srcdir)/config/arm/arm-cores.def
-OPTIONS_H_EXTRA += $(srcdir)/config/arm/arm-cores.def
+TM_H += $(srcdir)/config/arm/arm-cpu.h
 
 # All md files - except for arm.md.
 # This list should be kept in alphabetical order and updated whenever an md
@@ -67,18 +66,36 @@ MD_INCLUDES=	$(srcdir)/config/arm/arm1020e.md \
 s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
 	s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
 
-$(srcdir)/config/arm/arm-tune.md: $(srcdir)/config/arm/gentune.sh \
-	$(srcdir)/config/arm/arm-cores.def
-	$(SHELL) $(srcdir)/config/arm/gentune.sh \
-		$(srcdir)/config/arm/arm-cores.def > \
-		$(srcdir)/config/arm/arm-tune.md
+$(srcdir)/config/arm/arm-tune.md: $(srcdir)/config/arm/parsecpu.awk \
+	$(srcdir)/config/arm/arm-cpus.in
+	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=md \
+		$(srcdir)/config/arm/arm-cpus.in > arm-tune.new
+	mv arm-tune.new $(srcdir)/config/arm/arm-tune.md
 
-$(srcdir)/config/arm/arm-tables.opt: $(srcdir)/config/arm/genopt.sh \
-  $(srcdir)/config/arm/arm-cores.def $(srcdir)/config/arm/arm-arches.def \
-  $(srcdir)/config/arm/arm-fpus.def
-	$(SHELL) $(srcdir)/config/arm/genopt.sh $(srcdir)/config/arm > \
+$(srcdir)/config/arm/arm-tables.opt: $(srcdir)/config/arm/parsecpu.awk \
+  $(srcdir)/config/arm/arm-cpus.in
+	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=opt \
+		$(srcdir)/config/arm/arm-cpus.in > \
 		$(srcdir)/config/arm/arm-tables.opt
 
+$(srcdir)/config/arm/arm-cpu.h: $(srcdir)/config/arm/parsecpu.awk \
+  $(srcdir)/config/arm/arm-cpus.in
+	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=headers \
+		$(srcdir)/config/arm/arm-cpus.in > arm-cpu.new
+	mv arm-cpu.new $(srcdir)/config/arm/arm-cpu.h
+
+$(srcdir)/config/arm/arm-cpu-data.h: $(srcdir)/config/arm/parsecpu.awk \
+  $(srcdir)/config/arm/arm-cpus.in
+	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=data \
+		$(srcdir)/config/arm/arm-cpus.in > arm-cpu-data.new
+	mv arm-cpu-data.new $(srcdir)/config/arm/arm-cpu-data.h
+
+$(srcdir)/config/arm/arm-cpu-cdata.h: $(srcdir)/config/arm/parsecpu.awk \
+  $(srcdir)/config/arm/arm-cpus.in
+	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=common-data \
+		$(srcdir)/config/arm/arm-cpus.in > arm-cpu-cdata.new
+	mv arm-cpu-cdata.new $(srcdir)/config/arm/arm-cpu-cdata.h
+
 aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
     coretypes.h $(TM_H) $(TM_P_H) $(RTL_H) $(TREE_H) output.h $(C_COMMON_H)
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
@@ -92,8 +109,7 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
   $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
   $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
   intl.h libfuncs.h $(PARAMS_H) $(OPTS_H) sched-int.h \
-  $(srcdir)/config/arm/arm-cores.def \
-  $(srcdir)/config/arm/arm-arches.def $(srcdir)/config/arm/arm-fpus.def \
+  $(srcdir)/config/arm/arm-cpu-data.h \
   $(srcdir)/config/arm/arm-protos.h \
   $(srcdir)/config/arm/arm_neon_builtins.def \
   $(srcdir)/config/arm/arm_vfp_builtins.def
@@ -113,3 +129,5 @@ arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \
     coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H)
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/arm/arm-c.c
+
+arm-common.o: $(srcdir)/config/arm/arm-cpu-cdata.h
