diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index 8406fa0..c5002b3 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -2106,6 +2106,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "2", BASE_ARCH_2,
+    0,
     TARGET_CPU_arm2,
   },
   {
@@ -2116,6 +2117,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "2", BASE_ARCH_2,
+    0,
     TARGET_CPU_arm2,
   },
   {
@@ -2126,6 +2128,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "3", BASE_ARCH_3,
+    0,
     TARGET_CPU_arm6,
   },
   {
@@ -2136,6 +2139,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "3M", BASE_ARCH_3M,
+    0,
     TARGET_CPU_arm7m,
   },
   {
@@ -2146,6 +2150,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "4", BASE_ARCH_4,
+    0,
     TARGET_CPU_arm7tdmi,
   },
   {
@@ -2156,6 +2161,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "4T", BASE_ARCH_4T,
+    0,
     TARGET_CPU_arm7tdmi,
   },
   {
@@ -2166,6 +2172,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5", BASE_ARCH_5,
+    0,
     TARGET_CPU_arm10tdmi,
   },
   {
@@ -2176,6 +2183,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5T", BASE_ARCH_5T,
+    0,
     TARGET_CPU_arm10tdmi,
   },
   {
@@ -2186,6 +2194,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5E", BASE_ARCH_5E,
+    0,
     TARGET_CPU_arm1026ejs,
   },
   {
@@ -2196,6 +2205,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5TE", BASE_ARCH_5TE,
+    0,
     TARGET_CPU_arm1026ejs,
   },
   {
@@ -2206,6 +2216,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5TEJ", BASE_ARCH_5TEJ,
+    0,
     TARGET_CPU_arm1026ejs,
   },
   {
@@ -2216,6 +2227,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6", BASE_ARCH_6,
+    0,
     TARGET_CPU_arm1136js,
   },
   {
@@ -2226,6 +2238,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6J", BASE_ARCH_6J,
+    0,
     TARGET_CPU_arm1136js,
   },
   {
@@ -2236,6 +2249,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6K", BASE_ARCH_6K,
+    0,
     TARGET_CPU_mpcore,
   },
   {
@@ -2246,6 +2260,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6Z", BASE_ARCH_6Z,
+    0,
     TARGET_CPU_arm1176jzs,
   },
   {
@@ -2256,6 +2271,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6KZ", BASE_ARCH_6KZ,
+    0,
     TARGET_CPU_arm1176jzs,
   },
   {
@@ -2266,6 +2282,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6KZ", BASE_ARCH_6KZ,
+    0,
     TARGET_CPU_arm1176jzs,
   },
   {
@@ -2276,6 +2293,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6T2", BASE_ARCH_6T2,
+    0,
     TARGET_CPU_arm1156t2s,
   },
   {
@@ -2286,6 +2304,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6M", BASE_ARCH_6M,
+    'M',
     TARGET_CPU_cortexm1,
   },
   {
@@ -2296,6 +2315,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "6M", BASE_ARCH_6M,
+    'M',
     TARGET_CPU_cortexm1,
   },
   {
@@ -2306,6 +2326,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7", BASE_ARCH_7,
+    0,
     TARGET_CPU_cortexa8,
   },
   {
@@ -2316,6 +2337,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7A", BASE_ARCH_7A,
+    'A',
     TARGET_CPU_cortexa8,
   },
   {
@@ -2326,6 +2348,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7A", BASE_ARCH_7A,
+    'A',
     TARGET_CPU_cortexa8,
   },
   {
@@ -2336,6 +2359,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7R", BASE_ARCH_7R,
+    'R',
     TARGET_CPU_cortexr4,
   },
   {
@@ -2346,6 +2370,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7M", BASE_ARCH_7M,
+    'M',
     TARGET_CPU_cortexm3,
   },
   {
@@ -2356,6 +2381,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "7EM", BASE_ARCH_7EM,
+    'M',
     TARGET_CPU_cortexm4,
   },
   {
@@ -2366,6 +2392,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "8A", BASE_ARCH_8A,
+    'A',
     TARGET_CPU_cortexa53,
   },
   {
@@ -2376,6 +2403,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "8A", BASE_ARCH_8A,
+    'A',
     TARGET_CPU_cortexa53,
   },
   {
@@ -2386,6 +2414,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "8A", BASE_ARCH_8A,
+    'A',
     TARGET_CPU_cortexa53,
   },
   {
@@ -2396,6 +2425,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "8M_BASE", BASE_ARCH_8M_BASE,
+    'M',
     TARGET_CPU_cortexm23,
   },
   {
@@ -2406,6 +2436,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "8M_MAIN", BASE_ARCH_8M_MAIN,
+    'M',
     TARGET_CPU_cortexm7,
   },
   {
@@ -2416,6 +2447,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5TE", BASE_ARCH_5TE,
+    0,
     TARGET_CPU_iwmmxt,
   },
   {
@@ -2426,6 +2458,7 @@ const arch_option all_architectures[] =
       isa_nobit
     },
     "5TE", BASE_ARCH_5TE,
+    0,
     TARGET_CPU_iwmmxt2,
   },
   {{NULL, NULL, {isa_nobit}},
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 43f4ebc..3231740 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -46,6 +46,7 @@
 #   tune for <cpu>
 #   [tune flags <list>]
 #   base <name>
+#   [profile <A|R|M>]
 #   isa <isa-flags-list>
 # end arch <name>
 #
@@ -211,12 +212,14 @@ end arch armv6t2
 begin arch armv6-m
  tune for cortex-m1
  base 6M
+ profile M
  isa ARMv6m
 end arch armv6-m
 
 begin arch armv6s-m
  tune for cortex-m1
  base 6M
+ profile M
  isa ARMv6m
 end arch armv6s-m
 
@@ -235,6 +238,7 @@ begin arch armv7-a
  tune for cortex-a8
  tune flags CO_PROC
  base 7A
+ profile A
  isa ARMv7a
 # fp => VFPv3-d16, simd => neon-vfpv3
  option fp	       add VFPv3 FP_DBL
@@ -257,6 +261,7 @@ begin arch armv7ve
  tune for cortex-a8
  tune flags CO_PROC
  base 7A
+ profile A
  isa ARMv7ve
 # fp => VFPv4-d16, simd => neon-vfpv4
  option vfpv3-d16      add VFPv3 FP_DBL
@@ -279,6 +284,7 @@ begin arch armv7-r
  tune for cortex-r4
  tune flags CO_PROC
  base 7R
+ profile R
  isa ARMv7r
 # ARMv7-r uses VFPv3-d16
  option fp.sp add VFPv3
@@ -294,6 +300,7 @@ begin arch armv7-m
  tune for cortex-m3
  tune flags CO_PROC
  base 7M
+ profile M
  isa ARMv7m
 # In theory FP is permitted in v7-m, but in practice no implementations exist.
 # leave it out for now.
@@ -303,6 +310,7 @@ begin arch armv7e-m
  tune for cortex-m4
  tune flags CO_PROC
  base 7EM
+ profile M
  isa ARMv7em
 # fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16
  option fp add VFPv4
@@ -317,6 +325,7 @@ begin arch armv8-a
  tune for cortex-a53
  tune flags CO_PROC
  base 8A
+ profile A
  isa ARMv8a
  option crc add bit_crc32
  option simd add FP_ARMv8 NEON
@@ -329,6 +338,7 @@ begin arch armv8.1-a
  tune for cortex-a53
  tune flags CO_PROC
  base 8A
+ profile A
  isa ARMv8_1a
  option simd add FP_ARMv8 NEON
  option crypto add FP_ARMv8 CRYPTO
@@ -340,6 +350,7 @@ begin arch armv8.2-a
  tune for cortex-a53
  tune flags CO_PROC
  base 8A
+ profile A
  isa ARMv8_2a
  option simd add FP_ARMv8 NEON
  option fp16 add bit_fp16 FP_ARMv8 NEON
@@ -351,6 +362,7 @@ end arch armv8.2-a
 begin arch armv8-m.base
  tune for cortex-m23
  base 8M_BASE
+ profile M
  isa ARMv8m_base
 end arch armv8-m.base
 
@@ -358,6 +370,7 @@ begin arch armv8-m.main
  tune for cortex-m7
  tune flags CO_PROC
  base 8M_MAIN
+ profile M
  isa ARMv8m_main
  option dsp add bit_ARMv7em
 # fp => FPv5-sp-d16; fp.dp => FPv5-d16
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 25210e2..94fbcf0 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -464,6 +464,8 @@ struct arm_build_target
   const char *arch_pp_name;
   /* The base architecture value.  */
   enum base_architecture base_arch;
+  /* The profile letter for the architecture, upper case by convention.  */
+  char profile;
   /* Bitmap encapsulating the isa_bits for the target environment.  */
   sbitmap isa;
   /* Flags used for tuning.  Long term, these move into tune_params.  */
@@ -507,6 +509,8 @@ struct arch_option
   const char *arch;
   /* Base architecture, from which this specific architecture is derived.  */
   enum base_architecture base_arch;
+  /* The profile letter for the architecture, upper case by convention.  */
+  const char profile;
   /* Default tune target (in the absence of any more specific data).  */
   enum processor_type tune_id;
 };
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c00bdd8..d3a40b9 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3273,6 +3273,7 @@ arm_configure_build_target (struct arm_build_target *target,
   /* Finish initializing the target structure.  */
   target->arch_pp_name = arm_selected_arch->arch;
   target->base_arch = arm_selected_arch->base_arch;
+  target->profile = arm_selected_arch->profile;
 
   target->tune_flags = tune_data->tune_flags;
   target->tune = tune_data->tune;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 43d4477..6bc36bba 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2189,13 +2189,7 @@ extern int making_const_table;
 /* Expands to an upper-case char of the target's architectural
    profile.  */
 #define TARGET_ARM_ARCH_PROFILE				\
-  (!arm_arch_notm					\
-    ? 'M'						\
-    : (arm_arch7					\
-      ? (strlen (arm_arch_name) >=3			\
-	? (arm_arch_name[strlen (arm_arch_name) - 3])	\
-      	: 0)						\
-      : 0))
+  (arm_active_target.profile)
 
 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
    Bit 0 for bytes, up to bit 3 for double-words.  */
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index b6e5093..d38d664 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -299,6 +299,12 @@ function gen_comm_data () {
 	# arch, base_arch
 	print "    \"" arch_base[archs[n]] "\", BASE_ARCH_" \
 	    arch_base[archs[n]] ","
+	# profile letter code, or zero if none.
+	if (archs[n] in arch_prof) {
+	    print "    \'" arch_prof[archs[n]] "\',"
+	} else {
+	    print "    0,"
+	}
 	# tune_id
 	print "    TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] ","
 	print "  },"
@@ -477,6 +483,12 @@ BEGIN {
     parse_ok = 1
 }
 
+/^[ 	]*profile / {
+    if (arch_name == "") fatal("\"profile\" statement outside of arch block")
+    arch_prof[arch_name] = $2
+    parse_ok = 1
+}
+
 /^end arch / {
     if (arch_name != $3) fatal("mimatched end arch")
     if (! arch_name in arch_tune_for) {
