From patchwork Tue Jun 28 14:56:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 2359 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 31D81240F1 for ; Tue, 28 Jun 2011 14:56:04 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id D5139A18355 for ; Tue, 28 Jun 2011 14:56:03 +0000 (UTC) Received: by qwb8 with SMTP id 8so201423qwb.11 for ; Tue, 28 Jun 2011 07:56:03 -0700 (PDT) Received: by 10.229.63.144 with SMTP id b16mr5779059qci.80.1309272963130; Tue, 28 Jun 2011 07:56:03 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs10580qcf; Tue, 28 Jun 2011 07:56:02 -0700 (PDT) Received: by 10.52.73.65 with SMTP id j1mr10414410vdv.248.1309272961865; Tue, 28 Jun 2011 07:56:01 -0700 (PDT) Received: from mail-qy0-f178.google.com (mail-qy0-f178.google.com [209.85.216.178]) by mx.google.com with ESMTPS id dk1si292758vdb.124.2011.06.28.07.56.01 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 28 Jun 2011 07:56:01 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by qyk27 with SMTP id 27so202119qyk.16 for ; Tue, 28 Jun 2011 07:56:01 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.129.148 with SMTP id o20mr6131717qas.395.1309272961213; Tue, 28 Jun 2011 07:56:01 -0700 (PDT) Received: by 10.224.47.134 with HTTP; Tue, 28 Jun 2011 07:56:01 -0700 (PDT) In-Reply-To: <1309270853-24353-1-git-send-email-ramana.radhakrishnan@linaro.org> References: <1309270853-24353-1-git-send-email-ramana.radhakrishnan@linaro.org> Date: Tue, 28 Jun 2011 15:56:01 +0100 Message-ID: Subject: Re: [PATCH] [ARM] Fix constraint modifiers for VFP patterns. From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Cc: patches@linaro.org, rearnsha@arm.com, Ramana Radhakrishnan On 28 June 2011 15:20, Ramana Radhakrishnan wrote: > Hi, > > Sometime back Chung-Lin noticed that a few of the VFP patterns as below > had the '+' constraint modifiers rather than the '=' constraint > modifiers. > > I've now corrected this as follows and tested this on trunk with arm-linux-gnueabi > and qemu for a v7-a neon test run. Committed. I just noticed that the patch that I sent out had an unrelated change to arm.h while what I actually tested and committed was without that hunk. Attached is what I actually committed. Phew. cheers Ramana 2011-06-28 Ramana Radhakrishnan * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier with '=' constraint modifier. (*divdf3_vfp): Likewise. ("*mulsf3_vfp"): Likewise. ("*muldf3_vfp"): Likewise. ("*mulsf3negsf_vfp"): Likewise. ("*muldf3negdf_vfp"): Likewise. Index: gcc/config/arm/vfp.md =================================================================== --- gcc/config/arm/vfp.md (revision 175585) +++ gcc/config/arm/vfp.md (working copy) @@ -719,7 +719,7 @@ ;; Division insns (define_insn "*divsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (div:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -729,7 +729,7 @@ ) (define_insn "*divdf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (div:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -742,7 +742,7 @@ ;; Multiplication insns (define_insn "*mulsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -752,7 +752,7 @@ ) (define_insn "*muldf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -761,9 +761,8 @@ (set_attr "type" "fmuld")] ) - (define_insn "*mulsf3negsf_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -773,7 +772,7 @@ ) (define_insn "*muldf3negdf_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"