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[91.76.180.33]) by mx.google.com with ESMTPSA id i13sm51995lab.38.2015.02.26.01.08.21 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Feb 2015 01:08:22 -0800 (PST) Mime-Version: 1.0 (Mac OS X Mail 8.2 \(2070.6\)) Subject: Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney From: Maxim Kuvyrkov In-Reply-To: <54EECE57.5020105@marvell.com> Date: Thu, 26 Feb 2015 12:07:50 +0300 Cc: James Greenhalgh , Nick Clifton , Paul Brook , Ramana Radhakrishnan , Richard Earnshaw , Kyrylo Tkachov , "gcc-patches@gcc.gnu.org" , Xinyu Qi , Liping Gao Message-Id: References: <5493DF85.6050309@marvell.com> <20141219093534.GA26486@arm.com> <5493FE08.1050309@marvell.com> <549405FF.3050106@marvell.com> <54EDD14F.3010508@marvell.com> <20150225142032.GA10515@arm.com> <54EECE57.5020105@marvell.com> To: Xingxing Pan X-Original-Sender: maxim.kuvyrkov@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::229 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 > On Feb 26, 2015, at 10:42 AM, Xingxing Pan wrote: ... > Expand several arm types. > > 2015-02-26 Xingxing Pan > > * config/arm/types.md: > (neon_logic): Expand to neon_logic_reg and neon_logic_imm. > (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. > (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. > (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. > (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. > (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. > * config/aarch64/aarch64-simd.md: Ditto. > * config/aarch64/aarch64.md: Ditto. > * config/aarch64/thunderx.md: Ditto. > * config/arm/arm.md: Ditto. > * config/arm/cortex-a15-neon.md: Ditto. > * config/arm/cortex-a17-neon.md: Ditto. > * config/arm/cortex-a57.md: Ditto. > * config/arm/cortex-a8-neon.md: Ditto. > * config/arm/cortex-a9-neon.md: Ditto. > * config/arm/marvell-whitney.md: Ditto. > * config/arm/neon.md: Ditto. > * config/arm/xgene1.md: Ditto. I think you are going overkill with this approach. Instead of encoding operand types in _ values, it seems simpler to add a new operand_type attribute and set it on affected insns. (define_attr "op_type" "imm,reg,scalar,other" (const_string "other)) then in define_insn (example from first hunk of your patch): [(set_attr "type" "neon_load1_1reg, neon_store1_1reg,\ neon_logic, neon_to_gp, neon_from_gp,\ mov_reg, neon_move") (set_attr "op_type" "*, *,\ reg, scalar, scalar,\ *, *")] and then in define_insn_reservation: (const_string "wTP43") (eq_attr "type" "neon_arith_acc,neon_shift_acc") (if_then_else (match_test The point of this is that definitions of many architectures that don't care about operand type don't need to change. --- Maxim Kuvyrkov www.linaro.org --- a/gcc/config/arm/marvell-whitney.md +++ b/gcc/config/arm/marvell-whitney.md @@ -170,7 +170,7 @@ (const_string "wTP41") (eq_attr "type" "neon_permute_q,neon_zip_q") (const_string "wTP42") (eq_attr "type" "neon_bsl") (const_string "wTP43") (and (eq_attr "type" "neon_logic") (eq_attr "op_type" "imm"))