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[209.132.180.131]) by mx.google.com with ESMTPS id y62si21866527pgy.100.2016.10.15.23.01.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Oct 2016 23:01:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-438721-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-438721-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-438721-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=ICuUox2hiO9hSwMdBKFObUr38mMvbJ8QWXekSBFyQfJx6A 3Ae7PIRj6gyYMlB21m8QOjmA6Rvky0v6rJ+EuEKNwtWgLDHhkPsk+jSokY/X6b/8 twfdU0kam2YXCA3SYGYwI8OQ18kNC4mrvQ4lAqvdLk4LJu8jFC1yao9YD1br0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=5XXpymN1HVNfXxiyK8KA71wF+Tg=; b=jb87k6k5jOd/J2HC+4+J U377wCR6nzZH8GwetlAkhXzeZW/hrkG0WqNtSl4+c6h3+Qy/hZFDPnx2P1epuNqL X70LO7c2HdQlGCEbkwjz9pLPuzhrNSFmMpPrEQY/mscE6GyjQqLCpD30zM4qclWh c9nCJXaUIr6tHsa0uJTyEHM= Received: (qmail 15042 invoked by alias); 16 Oct 2016 06:00:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14953 invoked by uid 89); 16 Oct 2016 06:00:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, KAM_MANYTO, RCVD_IN_DNSWL_LOW, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:check_n, thumb-1, thumb1, Thumb1 X-HELO: mail-it0-f50.google.com Received: from mail-it0-f50.google.com (HELO mail-it0-f50.google.com) (209.85.214.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 16 Oct 2016 06:00:36 +0000 Received: by mail-it0-f50.google.com with SMTP id o19so24924740ito.1 for ; Sat, 15 Oct 2016 23:00:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=g5OayTgLrnCWvmN/RgkSQzaAStxjD0s4+sV/f3mDIrM=; b=WuciH+zKL4+YEo8+80BmlaA4fg5QBVDcHQG7ZaB8a5ZWSp66hFRTcxUC2LU0AAzEEF es4KSdnRrd+cBA0qCTk8H+ydsKrULdCycTgJjrF9Nfx3dTZNshdXYlvuswugqpjNZrVG ExxzcExTgOKIt59SY9GTiV58dUkY01nHZPUgh2U+m9IEXFe/7RL1LgXqapGyXDJfvwCj 6ftGh2zMH87V8UtNab2L5nOAucJON/sPAWqB1LWhwOKpONXWV77z64YTzz86g4cHifYD rhdgFewnwHq4r3HIRNVLexBhboKD2uwG7l1aVRU0zMhGdCHcVlCR7gEzd3xijASHfxHU pVcQ== X-Gm-Message-State: AA6/9RmtBmCFC7f0MGggtxwse5+Om7XIajTlyD+qBI1Vgt1gwv3l7MlH0hPRnEst+mU1P6z6WxhwOyL4UlylekRd X-Received: by 10.36.135.201 with SMTP id f192mr4182680ite.13.1476597634075; Sat, 15 Oct 2016 23:00:34 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.112.78 with HTTP; Sat, 15 Oct 2016 23:00:33 -0700 (PDT) From: Prathamesh Kulkarni Date: Sun, 16 Oct 2016 11:30:33 +0530 Message-ID: Subject: RFC [2/3] divmod transform v2 - override expand_divmod_libfunc for ARM port To: gcc Patches , Richard Biener , Kugan , Jim Wilson , Ramana Radhakrishnan , Kyrill Tkachov X-IsSubscribed: yes Hi, This patch overrides expand_divmod_libfunc hook for ARM port. I separated the SImode tests into separate file from DImode tests because certain arm configs (cortex-15) have hardware div insn for SImode but not for DImode, and for that config we want SImode tests to be disabled but not DImode tests. The patch therefore has two target-effective checks: divmod and divmod_simode. Cross-tested on arm*-*-*. OK to commit ? Thanks, Prathamesh 2016-10-15 Prathamesh Kulkarni Kugan Vivekanandarajah Jim Wilson * config/arm/arm.c (arm_expand_divmod_libfunc): Override hook TARGET_EXPAND_DIVMOD_LIBFUNC. * doc/sourcebuild.texi: Add items for arm_divmod_simode, divmod, divmod_simode. testsuite/ * lib/target-supports.exp (check_effective_target_divmod): New. (check_effective_target_divmod_simode): Likewise. (check_effective_target_arm_divmod_simode): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 39e3aa8..b1a6aeb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -62,6 +62,7 @@ #include "builtins.h" #include "tm-constrs.h" #include "rtl-iter.h" +#include "optabs-libfuncs.h" /* This file should be included last. */ #include "target-def.h" @@ -304,6 +305,7 @@ static section *arm_function_section (tree, enum node_frequency, bool, bool); static bool arm_asm_elf_flags_numeric (unsigned int flags, unsigned int *num); static unsigned int arm_elf_section_type_flags (tree decl, const char *name, int reloc); +static void arm_expand_divmod_libfunc (rtx, machine_mode, rtx, rtx, rtx *, rtx *); /* Table of machine attributes. */ static const struct attribute_spec arm_attribute_table[] = @@ -739,6 +741,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_SECTION_TYPE_FLAGS #define TARGET_SECTION_TYPE_FLAGS arm_elf_section_type_flags +#undef TARGET_EXPAND_DIVMOD_LIBFUNC +#define TARGET_EXPAND_DIVMOD_LIBFUNC arm_expand_divmod_libfunc + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -30776,4 +30781,33 @@ arm_elf_section_type_flags (tree decl, const char *name, int reloc) return flags; } +/* Generate call to __aeabi_[mode]divmod (op0, op1). */ + +static void +arm_expand_divmod_libfunc (rtx libfunc, machine_mode mode, + rtx op0, rtx op1, + rtx *quot_p, rtx *rem_p) +{ + if (mode == SImode) + gcc_assert (!TARGET_IDIV); + + machine_mode libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), + MODE_INT); + + rtx libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, + libval_mode, 2, + op0, GET_MODE (op0), + op1, GET_MODE (op1)); + + rtx quotient = simplify_gen_subreg (mode, libval, libval_mode, 0); + rtx remainder = simplify_gen_subreg (mode, libval, libval_mode, + GET_MODE_SIZE (mode)); + + gcc_assert (quotient); + gcc_assert (remainder); + + *quot_p = quotient; + *rem_p = remainder; +} + #include "gt-arm.h" diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 07c75e2..39de0ff 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1675,6 +1675,10 @@ and @code{MOVT} instructions available. ARM target generates Thumb-1 code for @code{-mthumb} with @code{CBZ} and @code{CBNZ} instructions available. +@item arm_divmod_simode +ARM target for which divmod transform is disabled, if it supports hardware +div instruction. + @end table @subsubsection AArch64-specific attributes @@ -1848,6 +1852,13 @@ Target requires a command line argument to enable a SIMD instruction set. @item pie_copyreloc The x86-64 target linker supports PIE with copy reloc. + +@item divmod +Target supporting hardware divmod insn or divmod libcall. + +@item divmod_simode +Target supporting hardware divmod insn or divmod libcall for SImode. + @end table @subsubsection Environment attributes diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 201ed4b..fc5e37f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8070,3 +8070,41 @@ proc check_effective_target_profile_update_atomic {} { int main (void) { return 0; } } "-fprofile-update=atomic -fprofile-generate"] } + +#For versions of ARM architectures that have hardware div insn, +#disable the divmod transform + +proc check_effective_target_arm_divmod_simode { } { + return [check_no_compiler_messages arm_divmod assembly { + #ifdef __ARM_ARCH_EXT_IDIV__ + #error has div insn + #endif + int i; + }] +} + +# Return 1 if target supports divmod hardware insn or divmod libcall. + +proc check_effective_target_divmod { } { + #TODO: Add checks for all targets that have either hardware divmod insn + # or define libfunc for divmod. + if { [istarget arm*-*-*] + || [istarget x86_64-*-*] } { + return 1 + } + return 0 +} + +# Return 1 if target supports divmod for SImode. The reason for +# separating this from check_effective_target_divmod is that +# some versions of ARM architecture define div instruction +# only for simode, and for these archs, we do not want to enable +# divmod transform for simode. + +proc check_effective_target_divmod_simode { } { + if { [istarget arm*-*-*] } { + return [check_effective_target_arm_divmod_simode] + } + + return [check_effective_target_divmod] +}