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[209.132.180.131]) by mx.google.com with ESMTPS id nk17si5458649pdb.26.2015.05.22.16.24.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 16:24:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-398743-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 35026 invoked by alias); 22 May 2015 23:24:04 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 35016 invoked by uid 89); 22 May 2015 23:24:03 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.7 required=5.0 tests=AWL, BAYES_50, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qg0-f53.google.com Received: from mail-qg0-f53.google.com (HELO mail-qg0-f53.google.com) (209.85.192.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 22 May 2015 23:24:02 +0000 Received: by qgew3 with SMTP id w3so17682874qge.2 for ; Fri, 22 May 2015 16:24:00 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.229.98.200 with SMTP id r8mr14761016qcn.15.1432337040073; Fri, 22 May 2015 16:24:00 -0700 (PDT) Received: by 10.140.104.171 with HTTP; Fri, 22 May 2015 16:23:59 -0700 (PDT) Date: Fri, 22 May 2015 16:24:00 -0700 Message-ID: Subject: [PATCH, AARCH64] make stdarg functions work with +nofp From: Jim Wilson To: "gcc-patches@gcc.gnu.org" X-Original-Sender: jim.wilson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 The compiler currently ICEs when compiling a stdarg function with +nofp, as reported in PR 66258. The aarch64.md file disables FP instructions using TARGET_FLOAT, which supports both -mgeneral-regs-only and +nofp. But there is code in aarch64.c that checks TARGET_GENERAL_REGS_ONLY. This results in FP instructions when using +nofp, The aarch64.c code needs to use TARGET_FLOAT instead like the md file already does. I can't meaningfully test this with a bootstrap, since the patch has no effect unless I bootstrap with +nofp, and that will fail as gcc contains floating point code. The testsuite already has multiple stdarg tests, so there is no need for another one. I tested this by verifying I get the same results for some simple testcasess with and without the patch, with and without using -mgeneral-regs-only and -mcpu=cortex-a53+nofp. 2015-05-22 Jim Wilson PR target/66258 * config/aarch64/aarch64.c (aarch64_function_value_regno_p): Change !TARGET_GENERAL_REGS_ONLY to TARGET_FLOAT. (aarch64_secondary_reload): Likewise (aarch64_expand_builtin_va_start): Change TARGET_GENERAL_REGS_ONLY to !TARGET_FLOAT. (aarch64_gimplify_va_arg_expr, aarch64_setup_incoming_varargs): Likewise. Index: config/aarch64/aarch64.c =================================================================== --- config/aarch64/aarch64.c (revision 223590) +++ config/aarch64/aarch64.c (working copy) @@ -1666,7 +1666,7 @@ aarch64_function_value_regno_p (const un /* Up to four fp/simd registers can return a function value, e.g. a homogeneous floating-point aggregate having four members. */ if (regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS) - return !TARGET_GENERAL_REGS_ONLY; + return TARGET_FLOAT; return false; } @@ -4783,7 +4783,7 @@ aarch64_secondary_reload (bool in_p ATTR /* A TFmode or TImode memory access should be handled via an FP_REGS because AArch64 has richer addressing modes for LDR/STR instructions than LDP/STP instructions. */ - if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS + if (TARGET_FLOAT && rclass == GENERAL_REGS && GET_MODE_SIZE (mode) == 16 && MEM_P (x)) return FP_REGS; @@ -7571,7 +7571,7 @@ aarch64_expand_builtin_va_start (tree va vr_save_area_size = (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG; - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) { if (cum->aapcs_nvrn > 0) sorry ("%qs and floating point or vector arguments", @@ -7681,7 +7681,7 @@ aarch64_gimplify_va_arg_expr (tree valis &is_ha)) { /* TYPE passed in fp/simd registers. */ - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) sorry ("%qs and floating point or vector arguments", "-mgeneral-regs-only"); @@ -7918,7 +7918,7 @@ aarch64_setup_incoming_varargs (cumulati gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn; vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn; - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) { if (local_cum.aapcs_nvrn > 0) sorry ("%qs and floating point or vector arguments",