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[209.132.180.131]) by mx.google.com with ESMTPS id xs3si1674367pbb.215.2015.06.12.13.43.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Jun 2015 13:43:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-400413-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 111952 invoked by alias); 12 Jun 2015 20:43:44 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 111943 invoked by uid 89); 12 Jun 2015 20:43:43 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qk0-f175.google.com Received: from mail-qk0-f175.google.com (HELO mail-qk0-f175.google.com) (209.85.220.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 12 Jun 2015 20:43:42 +0000 Received: by qkx62 with SMTP id 62so22303275qkx.3 for ; Fri, 12 Jun 2015 13:43:40 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.55.22.4 with SMTP id g4mr34552984qkh.10.1434141820302; Fri, 12 Jun 2015 13:43:40 -0700 (PDT) Received: by 10.140.101.67 with HTTP; Fri, 12 Jun 2015 13:43:40 -0700 (PDT) Date: Fri, 12 Jun 2015 13:43:40 -0700 Message-ID: Subject: [PATCH, AARCH64] movi type attribute confusion From: Jim Wilson To: "gcc-patches@gcc.gnu.org" X-Original-Sender: jim.wilson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22d as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 We have 5 patterns that can emit the movi instruction. These patterns map it to 4 different type attributes. The mov_aarch64 pattern uses mov_imm. The movdi_aarch64 pattern uses fmov. The movtf_aarch64 pattern uses fconstd. And the two aarch64_simd_mov patterns for VD and VQ use neon_move. Bitwise identical instructions should always map to the same attribute type, so we need to change these patterns to agree on the right attribute. movi is an integer simd instruction, so neon_move is the only choice that makes sense. The following patch corrects the first 3 patterns to use neon_move like the last two. We could optionally create a new type attribute, e.g. neon_move_imm. I can do that if people think it would be better. This patch was tested with a make bootstrap and make check on an APM box running Ubuntu 14.04. FYI This patch overlaps with my movtf-zero patch which is still waiting review, but the overlap is trivial to resolve so this should not be a problem. Jim 2015-06-12 Jim Wilson * config/aarch64/aarch64.md (mov_aarch64): Change alternative 2 to use neon_move instead of mov_imm. (movdi_aarch64): Change alternative 14 to use neon_move not fmov. (movtf_aarch64): Change alternative 4 to use neon_move_q not fconstd. Index: config/aarch64/aarch64.md =================================================================== --- config/aarch64/aarch64.md (revision 224441) +++ config/aarch64/aarch64.md (working copy) @@ -827,7 +827,7 @@ (define_insn "*mov_aarch64" gcc_unreachable (); } } - [(set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ + [(set_attr "type" "mov_reg,mov_imm,neon_move,load1,load1,store1,store1,\ neon_to_gp,neon_from_gp,neon_dup") (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")] ) @@ -912,7 +912,7 @@ (define_insn_and_split "*movdi_aarch64" DONE; }" [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ - adr,adr,f_mcr,f_mrc,fmov,fmov") + adr,adr,f_mcr,f_mrc,fmov,neon_move") (set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) @@ -1063,7 +1063,7 @@ (define_insn "*movtf_aarch64" str\\t%q1, %0 ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0" - [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\ + [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,fconstd,\ f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*")