From patchwork Fri Jan 20 09:24:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 6313 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DBE1423E16 for ; Fri, 20 Jan 2012 09:24:23 +0000 (UTC) Received: from mail-we0-f180.google.com (mail-we0-f180.google.com [74.125.82.180]) by fiordland.canonical.com (Postfix) with ESMTP id CC9F6A188BD for ; Fri, 20 Jan 2012 09:24:23 +0000 (UTC) Received: by werm10 with SMTP id m10so285195wer.11 for ; Fri, 20 Jan 2012 01:24:23 -0800 (PST) Received: by 10.216.132.4 with SMTP id n4mr585960wei.19.1327051463676; Fri, 20 Jan 2012 01:24:23 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.223.110.140 with SMTP id n12cs3339fap; Fri, 20 Jan 2012 01:24:22 -0800 (PST) Received: by 10.182.0.106 with SMTP id 10mr25843350obd.72.1327051460408; Fri, 20 Jan 2012 01:24:20 -0800 (PST) Received: from mail-tul01m020-f178.google.com (mail-tul01m020-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id h8si542843obn.100.2012.01.20.01.24.19 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 Jan 2012 01:24:20 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by obbwc7 with SMTP id wc7so641862obb.37 for ; Fri, 20 Jan 2012 01:24:19 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.131.37 with SMTP id oj5mr26062386obb.63.1327051459621; Fri, 20 Jan 2012 01:24:19 -0800 (PST) Received: by 10.182.88.7 with HTTP; Fri, 20 Jan 2012 01:24:19 -0800 (PST) In-Reply-To: References: <20120118152621.GK18768@tyan-ft48-01.lab.bos.redhat.com> Date: Fri, 20 Jan 2012 09:24:19 +0000 Message-ID: Subject: Re: [Patch ARM] Fix PR50313 and handle PIC addresses properly. From: Ramana Radhakrishnan To: Jakub Jelinek Cc: gcc-patches , Patch Tracking This is what I finally committed to trunk. I'll backport this to 4.6 once I have finished testing it there. 2012-01-20 Ramana Radhakrishnan PR target/50313 * config/arm/arm.c (arm_load_pic_register): Use gen_pic_load_addr_unified. Delete calls to gen_pic_load_addr_32bit , gen_pic_add_dot_plus_eight and gen_pic_add_dot_plus_four. (arm_pic_static_addr): Likewise. (arm_rtx_costs_1): Adjust cost for UNSPEC_PIC_UNIFIED. (arm_note_pic_base): Handle UNSPEC_PIC_UNIFIED. * config/arm/arm.md (UNSPEC_PIC_UNIFIED): Define. (pic_load_addr_unified): New. ramana Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 183327) +++ gcc/config/arm/arm.c (working copy) @@ -5578,11 +5578,7 @@ if (TARGET_32BIT) { - emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx)); - if (TARGET_ARM) - emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); - else - emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); + emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); } else /* TARGET_THUMB1 */ { @@ -5595,10 +5591,10 @@ thumb_find_work_register (saved_regs)); emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); + emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); } else - emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); - emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); + emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); } } @@ -5628,20 +5624,7 @@ UNSPEC_SYMBOL_OFFSET); offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); - if (TARGET_32BIT) - { - emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); - if (TARGET_ARM) - insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); - else - insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); - } - else /* TARGET_THUMB1 */ - { - emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); - insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); - } - + insn = emit_insn (gen_pic_load_addr_unified (reg, offset_rtx, labelno)); return insn; } @@ -5684,7 +5667,7 @@ will_be_in_index_register (const_rtx x) { /* arm.md: calculate_pic_address will split this into a register. */ - return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; + return GET_CODE (x) == UNSPEC && (XINT (x, 1) == UNSPEC_PIC_SYM); } /* Return nonzero if X is a valid ARM state address operand. */ @@ -7648,6 +7631,15 @@ case SET: return false; + + case UNSPEC: + /* We cost this as high as our memory costs to allow this to + be hoisted from loops. */ + if (XINT (x, 1) == UNSPEC_PIC_UNIFIED) + { + *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); + } + return true; default: *total = COSTS_N_INSNS (4); @@ -10008,7 +10000,8 @@ arm_note_pic_base (rtx *x, void *date ATTRIBUTE_UNUSED) { if (GET_CODE (*x) == UNSPEC - && XINT (*x, 1) == UNSPEC_PIC_BASE) + && (XINT (*x, 1) == UNSPEC_PIC_BASE + || XINT (*x, 1) == UNSPEC_PIC_UNIFIED)) return 1; return 0; } Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 183327) +++ gcc/config/arm/arm.md (working copy) @@ -116,6 +116,7 @@ ; unaligned locations, on architectures which support ; that. UNSPEC_UNALIGNED_STORE ; Same for str/strh. + UNSPEC_PIC_UNIFIED ; Create a common pic addressing form. ]) ;; UNSPEC_VOLATILE Usage: @@ -5613,6 +5614,30 @@ "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];" ) +;; operand1 is the memory address to go into +;; pic_load_addr_32bit. +;; operand2 is the PIC label to be emitted +;; from pic_add_dot_plus_eight. +;; We do this to allow hoisting of the entire insn. +(define_insn_and_split "pic_load_addr_unified" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,l") + (unspec:SI [(match_operand:SI 1 "" "mX,mX,mX") + (match_operand:SI 2 "" "")] + UNSPEC_PIC_UNIFIED))] + "flag_pic" + "#" + "&& reload_completed" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_PIC_SYM)) + (set (match_dup 0) (unspec:SI [(match_dup 0) (match_dup 3) + (match_dup 2)] UNSPEC_PIC_BASE))] + "operands[3] = TARGET_THUMB ? GEN_INT (4) : GEN_INT (8);" + [(set_attr "type" "load1,load1,load1") + (set_attr "pool_range" "4096,4096,1024") + (set_attr "neg_pool_range" "4084,0,0") + (set_attr "arch" "a,t2,t1") + (set_attr "length" "8,6,4")] +) + ;; The rather odd constraints on the following are to force reload to leave ;; the insn alone, and to force the minipool generation pass to then move ;; the GOT symbol to memory.