From patchwork Wed May 9 12:55:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 8496 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0910123EB5 for ; Wed, 9 May 2012 12:55:21 +0000 (UTC) Received: from mail-qc0-f180.google.com (mail-qc0-f180.google.com [209.85.216.180]) by fiordland.canonical.com (Postfix) with ESMTP id ACD6EA18732 for ; Wed, 9 May 2012 12:55:20 +0000 (UTC) Received: by qcmv28 with SMTP id v28so157791qcm.11 for ; Wed, 09 May 2012 05:55:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=VxWXtGY+4f6E4NqZ7KSp13ltFo/nfJS/1NZt3WcIh1Y=; b=RdwBlgkZkQh4zsG1YBOL1Rf7SUyU74V33n6EU36aVBfiR0jDFCeeAlPFWWM6jpfin0 DbCT6RShEpdw2xFh4w7yFMQDj8P3/05Y0nSGnpUL5sddy6AyHmUFbkPLWzw9oIPT//8U Lx7P9+a6G0eiHW99G5UPSgXRbfwl4ZwzAKfh4y6v61yvwzFwa3vZn8dY/61EJgep9/Rq dlgxe9Fdsb1qCJadIV6cenKq9e9nEONsgQX87TBAIQKt2JkOmFwTNILTikWgC4eCwiOk ivlMa6ax3zT1nBJ8p67Hg1BD6P8fL0+voEs6sxcbglVzjJgdfbiPwynR+Tr7wQjiyD32 Oatg== Received: by 10.50.57.129 with SMTP id i1mr13079130igq.33.1336568119884; Wed, 09 May 2012 05:55:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.73.147 with SMTP id q19csp13382ibj; Wed, 9 May 2012 05:55:18 -0700 (PDT) Received: by 10.224.41.200 with SMTP id p8mr4932126qae.13.1336568118292; Wed, 09 May 2012 05:55:18 -0700 (PDT) Received: from mail-qa0-f43.google.com (mail-qa0-f43.google.com [209.85.216.43]) by mx.google.com with ESMTPS id q6si1061758qcy.139.2012.05.09.05.55.18 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 May 2012 05:55:18 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.43 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.43; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.43 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by qadb33 with SMTP id b33so1917649qad.16 for ; Wed, 09 May 2012 05:55:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.212.5 with SMTP id gq5mr5056150qab.1.1336568117906; Wed, 09 May 2012 05:55:17 -0700 (PDT) Received: by 10.224.95.196 with HTTP; Wed, 9 May 2012 05:55:17 -0700 (PDT) In-Reply-To: References: Date: Wed, 9 May 2012 13:55:17 +0100 Message-ID: Subject: Re: [RFC ivopts] ARM - Make ivopts take into account whether pre and post increments are actually supported on targets. From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Cc: Richard Guenther , Patch Tracking , Richard Earnshaw X-Gm-Message-State: ALoCoQkAyvp3T2UxhXDO21f46Bq1MobPyIzEDUcYadftsOT3dx4T0ei12QvFV14/aGz6WI747DVi > I would like another set of eyes on the backend specific changes - I > am currently regression testing this final version on FSF trunk. After testing and benchmarking and getting some private feedback about the patch, this is what I ended up committing. I have a follow up patch coming to adjust legitimate_address and friends for some of these modes. regards, Ramana 2012-05-09 Ramana Radhakrishnan * tree-ssa-loop-ivopts.c (add_autoinc_candidates, get_address_cost): Replace use of HAVE_{POST/PRE}_{INCREMENT/DECREMENT} with USE_{LOAD/STORE}_{PRE/POST}_{INCREMENT/DECREMENT} appropriately. * config/arm/arm.h (ARM_AUTOINC_VALID_FOR_MODE_P): New. (USE_LOAD_POST_INCREMENT): Define. (USE_LOAD_PRE_INCREMENT): Define. (USE_LOAD_POST_DECREMENT): Define. (USE_LOAD_PRE_DECREMENT): Define. (USE_STORE_PRE_DECREMENT): Define. (USE_STORE_PRE_INCREMENT): Define. (USE_STORE_POST_DECREMENT): Define. (USE_STORE_POST_INCREMENT): Define. (arm_auto_incmodes): Add enumeration. * config/arm/arm-protos.h (arm_autoinc_modes_ok_p): Declare. * config/arm/arm.c (arm_autoinc_modes_ok_p): Define. > > 2012-04-10  Ramana Radhakrishnan   > >        * tree-ssa-loop-ivopts.c (add_autoinc_candidates, get_address_cost): >        Replace use of HAVE_{POST/PRE}_{INCREMENT/DECREMENT} with >        USE_{LOAD/STORE}_{PRE/POST}_{INCREMENT/DECREMENT} appropriately. >        * config/arm/arm.h (ARM_AUTOINC_VALID_FOR_MODE_P): New. >        (USE_LOAD_POST_INCREMENT): Define. >        (USE_LOAD_PRE_INCREMENT): Define. >        (USE_LOAD_POST_DECREMENT): Define. >        (USE_LOAD_PRE_DECREMENT): Define. >        (USE_STORE_PRE_DECREMENT): Define. >        (USE_STORE_PRE_INCREMENT): Define. >        (USE_STORE_POST_DECREMENT): Define. >        (USE_STORE_POST_INCREMENT): Define. >        (arm_auto_incmodes): Add enumeration. >        * config/arm/arm-protos.h (arm_autoinc_modes_ok_p): Declare. >        * config/arm/arm.c (arm_autoinc_modes_ok_p): Define. >        (arm_rtx_costs_1): Adjust costs for >        auto-inc modes and pre / post modify in floating point mode. >        (arm_size_rtx_costs): Likewise. > > > regards, > Ramana > > > >> Richard. >> >>> Richard. >>> >>>> Ramana Index: gcc/tree-ssa-loop-ivopts.c =================================================================== --- gcc/tree-ssa-loop-ivopts.c (revision 187327) +++ gcc/tree-ssa-loop-ivopts.c (working copy) @@ -2362,8 +2362,12 @@ cstepi = int_cst_value (step); mem_mode = TYPE_MODE (TREE_TYPE (*use->op_p)); - if ((HAVE_PRE_INCREMENT && GET_MODE_SIZE (mem_mode) == cstepi) - || (HAVE_PRE_DECREMENT && GET_MODE_SIZE (mem_mode) == -cstepi)) + if (((USE_LOAD_PRE_INCREMENT (mem_mode) + || USE_STORE_PRE_INCREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == cstepi) + || ((USE_LOAD_PRE_DECREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == -cstepi)) { enum tree_code code = MINUS_EXPR; tree new_base; @@ -2380,8 +2384,12 @@ add_candidate_1 (data, new_base, step, important, IP_BEFORE_USE, use, use->stmt); } - if ((HAVE_POST_INCREMENT && GET_MODE_SIZE (mem_mode) == cstepi) - || (HAVE_POST_DECREMENT && GET_MODE_SIZE (mem_mode) == -cstepi)) + if (((USE_LOAD_POST_INCREMENT (mem_mode) + || USE_STORE_POST_INCREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == cstepi) + || ((USE_LOAD_POST_DECREMENT (mem_mode) + || USE_STORE_POST_DECREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == -cstepi)) { add_candidate_1 (data, base, step, important, IP_AFTER_USE, use, use->stmt); @@ -3315,25 +3323,29 @@ reg0 = gen_raw_REG (address_mode, LAST_VIRTUAL_REGISTER + 1); reg1 = gen_raw_REG (address_mode, LAST_VIRTUAL_REGISTER + 2); - if (HAVE_PRE_DECREMENT) + if (USE_LOAD_PRE_DECREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) { addr = gen_rtx_PRE_DEC (address_mode, reg0); has_predec[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_POST_DECREMENT) + if (USE_LOAD_POST_DECREMENT (mem_mode) + || USE_STORE_POST_DECREMENT (mem_mode)) { addr = gen_rtx_POST_DEC (address_mode, reg0); has_postdec[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_PRE_INCREMENT) + if (USE_LOAD_PRE_INCREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) { addr = gen_rtx_PRE_INC (address_mode, reg0); has_preinc[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_POST_INCREMENT) + if (USE_LOAD_POST_INCREMENT (mem_mode) + || USE_STORE_POST_INCREMENT (mem_mode)) { addr = gen_rtx_POST_INC (address_mode, reg0); has_postinc[mem_mode] Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 187327) +++ gcc/config/arm/arm.c (working copy) @@ -25886,5 +25886,51 @@ return ret; } - +bool +arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code) +{ + /* If we are soft float and we do not have ldrd + then all auto increment forms are ok. */ + if (TARGET_SOFT_FLOAT && (TARGET_LDRD || GET_MODE_SIZE (mode) <= 4)) + return true; + + switch (code) + { + /* Post increment and Pre Decrement are supported for all + instruction forms except for vector forms. */ + case ARM_POST_INC: + case ARM_PRE_DEC: + if (VECTOR_MODE_P (mode)) + { + if (code != ARM_PRE_DEC) + return true; + else + return false; + } + + return true; + + case ARM_POST_DEC: + case ARM_PRE_INC: + /* Without LDRD and mode size greater than + word size, there is no point in auto-incrementing + because ldm and stm will not have these forms. */ + if (!TARGET_LDRD && GET_MODE_SIZE (mode) > 4) + return false; + + /* Vector and floating point modes do not support + these auto increment forms. */ + if (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) + return false; + + return true; + + default: + return false; + + } + + return false; +} + #include "gt-arm.h" Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 187327) +++ gcc/config/arm/arm.h (working copy) @@ -1613,6 +1613,30 @@ #define HAVE_PRE_MODIFY_REG TARGET_32BIT #define HAVE_POST_MODIFY_REG TARGET_32BIT +enum arm_auto_incmodes + { + ARM_POST_INC, + ARM_PRE_INC, + ARM_POST_DEC, + ARM_PRE_DEC + }; + +#define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ + (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) +#define USE_LOAD_POST_INCREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) +#define USE_LOAD_PRE_INCREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) +#define USE_LOAD_POST_DECREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) +#define USE_LOAD_PRE_DECREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) + +#define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) +#define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) +#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) +#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) + /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. Index: gcc/config/arm/arm-protos.h =================================================================== --- gcc/config/arm/arm-protos.h (revision 187327) +++ gcc/config/arm/arm-protos.h (working copy) @@ -250,4 +250,6 @@ extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); +extern bool arm_autoinc_modes_ok_p (enum machine_mode, enum arm_auto_incmodes); + #endif /* ! GCC_ARM_PROTOS_H */