From patchwork Fri Aug 12 13:59:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 3431 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8846123F41 for ; Fri, 12 Aug 2011 13:59:40 +0000 (UTC) Received: from mail-qy0-f173.google.com (mail-qy0-f173.google.com [209.85.216.173]) by fiordland.canonical.com (Postfix) with ESMTP id 50687A1832B for ; Fri, 12 Aug 2011 13:59:40 +0000 (UTC) Received: by qyk31 with SMTP id 31so411000qyk.11 for ; Fri, 12 Aug 2011 06:59:39 -0700 (PDT) Received: by 10.229.16.200 with SMTP id p8mr650978qca.22.1313157579725; Fri, 12 Aug 2011 06:59:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.190.71 with SMTP id dh7cs151217qcb; Fri, 12 Aug 2011 06:59:39 -0700 (PDT) Received: from mr.google.com ([10.220.5.196]) by 10.220.5.196 with SMTP id 4mr300656vcw.207.1313157579260 (num_hops = 1); Fri, 12 Aug 2011 06:59:39 -0700 (PDT) Received: by 10.220.5.196 with SMTP id 4mr231798vcw.207.1313157578862; Fri, 12 Aug 2011 06:59:38 -0700 (PDT) Received: from mail-qw0-f50.google.com (mail-qw0-f50.google.com [209.85.216.50]) by mx.google.com with ESMTPS id f9si1957449vcb.88.2011.08.12.06.59.38 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 06:59:38 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.50 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.50 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by qwe5 with SMTP id 5so1887831qwe.37 for ; Fri, 12 Aug 2011 06:59:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.34.20 with SMTP id j20mr625858qad.60.1313157578218; Fri, 12 Aug 2011 06:59:38 -0700 (PDT) Received: by 10.224.89.67 with HTTP; Fri, 12 Aug 2011 06:59:38 -0700 (PDT) Date: Fri, 12 Aug 2011 14:59:38 +0100 Message-ID: Subject: [Patch ARM] Fix PR target/48328 part 1 From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking Hi, The Thumb2 tbh instruction can take half word values that are multiplied by 2 which implies the maximum offset is 0x1FFFF when you add it to the pc , rather than 0xFFF which is what the current range check of 0x2000 for HImode values indicates. Checked that a pre-compiled insn-recog.i that I had lying around got about 5 more tbh's *and* assembled and generally looks sane. Tests running for T2 v7-a on qemu. Will commit after results come out. cheers Ramana 2011-08-12 Ramana Radhakrishnan PR target/48328 * config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance for tbh instructions. : QImode)) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 869b9a9..0a6e6f2 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1906,7 +1906,7 @@ typedef struct : min >= -4096 && max < 4096 \ ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ : SImode) \ - : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ + : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ : (max >= 0x200) ? HImode \