From patchwork Wed Dec 14 11:44:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 5689 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4F48923E18 for ; Wed, 14 Dec 2011 11:44:26 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3BABAA183A9 for ; Wed, 14 Dec 2011 11:44:26 +0000 (UTC) Received: by eaak10 with SMTP id k10so405024eaa.11 for ; Wed, 14 Dec 2011 03:44:26 -0800 (PST) Received: by 10.205.129.137 with SMTP id hi9mr530041bkc.90.1323863066004; Wed, 14 Dec 2011 03:44:26 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs5991bkc; Wed, 14 Dec 2011 03:44:25 -0800 (PST) Received: by 10.236.93.4 with SMTP id k4mr11036010yhf.114.1323863064015; Wed, 14 Dec 2011 03:44:24 -0800 (PST) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id h69si1889228yhe.91.2011.12.14.03.44.23 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Dec 2011 03:44:23 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by ggnq4 with SMTP id q4so793880ggn.37 for ; Wed, 14 Dec 2011 03:44:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.193.41 with SMTP id hl9mr821170obc.44.1323863063391; Wed, 14 Dec 2011 03:44:23 -0800 (PST) Received: by 10.182.235.106 with HTTP; Wed, 14 Dec 2011 03:44:23 -0800 (PST) In-Reply-To: References: Date: Wed, 14 Dec 2011 11:44:23 +0000 Message-ID: Subject: Re: [Patch ARM] Call arm_legitimize_reload_address for TARGET_32BIT. From: Ramana Radhakrishnan To: gcc-patches Cc: Richard Earnshaw , Chung-Lin Tang , Patch Tracking And this time with the patch . 2011-12-14 Ramana Radhakrishnan * config/arm/arm.h (LEGITIMIZE_RELOAD_ADDRESS): Call arm_legitimize_reload_address for Thumb2 as well. Adjust call to thumb_legitimize_reload_address. * config/arm/arm-protos.h (thumb1_legitimize_reload_address): Renamed from thumb_legitimize_reload_address. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 296550a..1bbf855 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -59,7 +59,7 @@ extern int arm_legitimate_address_outer_p (enum machine_mode, rtx, RTX_CODE, int extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT); extern bool arm_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); -extern rtx thumb_legitimize_reload_address (rtx *, enum machine_mode, int, int, +extern rtx thumb1_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int); extern int arm_const_double_rtx (rtx); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 65b4e9d..8f21495 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6789,7 +6789,7 @@ arm_legitimize_reload_address (rtx *p, } rtx -thumb_legitimize_reload_address (rtx *x_p, +thumb1_legitimize_reload_address (rtx *x_p, enum machine_mode mode, int opnum, int type, int ind_levels ATTRIBUTE_UNUSED) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8a9ed1f..3cfe3e6 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1237,7 +1237,7 @@ enum reg_class operand. If we find one, push the reload and jump to WIN. This macro is used in only one place: `find_reloads_address' in reload.c. - For the ARM, we wish to handle large displacements off a base + For ARM and Thumb2, we wish to handle large displacements off a base register by splitting the addend across a MOV and the mem insn. This can cut the number of reloads needed. */ #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ @@ -1256,10 +1256,9 @@ enum reg_class /* We could probably achieve better results by defining PROMOTE_MODE to help cope with the variances between the Thumb's signed and unsigned byte and halfword load instructions. */ -/* ??? This should be safe for thumb2, but we may be able to do better. */ -#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ +#define THUMB1_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ do { \ - rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ + rtx new_x = thumb1_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ if (new_x) \ { \ X = new_x; \ @@ -1268,10 +1267,10 @@ do { \ } while (0) #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ - if (TARGET_ARM) \ + if (TARGET_32BIT) \ ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ else \ - THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) + THUMB1_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS.