From patchwork Mon Dec 12 20:10:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 5608 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EC6A723E0C for ; Mon, 12 Dec 2011 20:10:40 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id D767BA186C3 for ; Mon, 12 Dec 2011 20:10:40 +0000 (UTC) Received: by bke17 with SMTP id 17so7929520bke.11 for ; Mon, 12 Dec 2011 12:10:40 -0800 (PST) Received: by 10.204.156.208 with SMTP id y16mr10872824bkw.72.1323720640503; Mon, 12 Dec 2011 12:10:40 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs57996bkc; Mon, 12 Dec 2011 12:10:40 -0800 (PST) Received: by 10.101.200.30 with SMTP id c30mr4510571anq.108.1323720638003; Mon, 12 Dec 2011 12:10:38 -0800 (PST) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id i20si7800434ang.57.2011.12.12.12.10.37 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 12 Dec 2011 12:10:37 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by ggnq4 with SMTP id q4so6063631ggn.37 for ; Mon, 12 Dec 2011 12:10:37 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.11.104 with SMTP id p8mr3358011obb.24.1323720637130; Mon, 12 Dec 2011 12:10:37 -0800 (PST) Received: by 10.182.235.106 with HTTP; Mon, 12 Dec 2011 12:10:37 -0800 (PST) Date: Mon, 12 Dec 2011 20:10:37 +0000 Message-ID: Subject: [Patch ARM] Fix a latent issue in arm_print_operand From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking , Richard Earnshaw Hi, This fixes a latent issue in arm_print_operand where we would have generated a 128 bit alignment hint for any neon instruction that used the %A notation for printing memory addresses. Given that you can never have the load of a 64 bit quantity with an 128 bit alignment (indeed the list of instructions that I could think of that we might generate for this purpose is as below.) vld1.8 d0, [r0] vld1.16 d0, [r0] vld1.32 d0, [r0] vld1.64 d0, [r0] vld2.32 {d0[0], d1[0]}, [r0] vld4.16 {d0[0], d1[0], d2[0], D3[0]}, [r0] This is not an issue today for the following reasons : >From the list above: 1. The first 4 instructions will not come out of the compiler today (we put out vldr's or vldmia) instructions for auto-vectorized code. Indeed I found this only when I replaced the vldmia's and the vldr's with vld1's. 2. The last 2 instructions only come out of intrinsics. The first 4 will also get generated with the intrinsics but ..... we get away with this because of the type punning in arm_neon.h Even in the event we use this in that form, I doubt if we'll ever change that situation. I was able to trigger this when I tried to get the backend to generate vld1.64 instructions for appropriate vector modes instead of vldmia / vstmia in little endian configurations. (That will follow once testing completes) Ok ? cheers Ramana 2011-12-08 Ramana Radhakrishnan * config/arm/arm.c (arm_print_operand): Only allow hints of 128 bits for 16 byte loads. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d1d0c22..bfdac51 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -17654,8 +17654,8 @@ arm_print_operand (FILE *stream, rtx x, int code) /* Only certain alignment specifiers are supported by the hardware. */ if (memsize == 16 && (align % 32) == 0) align_bits = 256; - else if ((memsize == 8 || memsize == 16) && (align % 16) == 0) - align_bits = 128; + else if ((memsize == 16) && (align % 16) == 0) + align_bits = 128; else if ((align % 8) == 0) align_bits = 64; else