From patchwork Mon Jun 23 06:57:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 32321 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f198.google.com (mail-pd0-f198.google.com [209.85.192.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 698FD2055C for ; Mon, 23 Jun 2014 06:58:30 +0000 (UTC) Received: by mail-pd0-f198.google.com with SMTP id y10sf22423668pdj.9 for ; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:date:message-id:subject:from:to :x-original-sender:x-original-authentication-results:content-type; bh=N2OcaJkT3onkBM8rpk5GEZ5jxcNTzSyUrwmwZ6ZGvko=; b=PaKUzR2xerRDuSqMFtC3uADpSN+fIY3CISXDXgeMKFlWyB1N9ylMHTaHOddhoaBgj8 YAwgc/aLtdjOwq5GThZTywGIrQ40RR1ZN/+cScNlUaQBNAzjLRyc6Au4ueTaqX0bActN 8kiJ2O/LzLnFV/+RhzHyiCr/AlcZN41QIMvCmMVah7Dr14MjTzUESLgQ/U4n2SL1f1QV PoL54hcKFaMqIplI5WpqHDZLAS3BQiffRJyFxu/MgJBcb5JK6SUHEhvoAPSeWz+4j1uk cUQxn/e4aQV/nEUyMG6gMzG+bY7zKqEHNf++tgPXCzcHMagxGoZKhf8wNAp++nUls8tN r2JA== X-Gm-Message-State: ALoCoQmn0KrKztBxhEyuZ8GoEZ42eWSTOQF3TpuGFZCPKuHoQiPXQueG+dzo02gAQmbJzWQymEg5 X-Received: by 10.66.102.9 with SMTP id fk9mr8580953pab.2.1403506709674; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.106.99 with SMTP id d90ls1776249qgf.57.gmail; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-Received: by 10.58.29.16 with SMTP id f16mr18282490veh.23.1403506709581; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) Received: from mail-vc0-x22f.google.com (mail-vc0-x22f.google.com [2607:f8b0:400c:c03::22f]) by mx.google.com with ESMTPS id r1si8495110vda.16.2014.06.22.23.58.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 22 Jun 2014 23:58:29 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::22f as permitted sender) client-ip=2607:f8b0:400c:c03::22f; Received: by mail-vc0-f175.google.com with SMTP id hy4so5505574vcb.34 for ; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-Received: by 10.220.92.193 with SMTP id s1mr1713640vcm.34.1403506709388; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp109849vcb; Sun, 22 Jun 2014 23:58:29 -0700 (PDT) X-Received: by 10.68.211.164 with SMTP id nd4mr26287474pbc.44.1403506708689; Sun, 22 Jun 2014 23:58:28 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id rb7si20471399pbb.89.2014.06.22.23.58.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Jun 2014 23:58:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-370787-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 7942 invoked by alias); 23 Jun 2014 06:58:16 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 7924 invoked by uid 89); 23 Jun 2014 06:58:15 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f173.google.com Received: from mail-lb0-f173.google.com (HELO mail-lb0-f173.google.com) (209.85.217.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 06:57:46 +0000 Received: by mail-lb0-f173.google.com with SMTP id s7so3890980lbd.18 for ; Sun, 22 Jun 2014 23:57:42 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.19.164 with SMTP id g4mr15582600lae.47.1403506662858; Sun, 22 Jun 2014 23:57:42 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Sun, 22 Jun 2014 23:57:42 -0700 (PDT) Date: Mon, 23 Jun 2014 14:57:42 +0800 Message-ID: Subject: [PATCH, 2/10] prepare ccmp From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, The patch makes several functions global, which will be used when expanding ccmp instructions. The other change in this patch is to check CCMP when turning code into jumpy sequence. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * cfgexpand.c (expand_gimple_cond): Check conditional compare. * expmed.c (emit_cstore): Make it global. * expmed.h: #include "insn-codes.h". (emit_cstore): New prototype. * expr.c (expand_operands): Make it global. * expr.h (expand_operands): New prototype. * optabs.c (get_rtx_code): Make it global and return CODE for BIT_AND_EXPR and BIT_IOR_EXPR. * optabs.h (get_rtx_code): New prototype. extern rtx expand_binop (enum machine_mode, optab, rtx, rtx, rtx, int, diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index e8cd87f..a32e1b3 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -2095,9 +2095,10 @@ expand_gimple_cond (basic_block bb, gimple stmt) op0 = gimple_assign_rhs1 (second); op1 = gimple_assign_rhs2 (second); } - /* If jumps are cheap turn some more codes into - jumpy sequences. */ - else if (BRANCH_COST (optimize_insn_for_speed_p (), false) < 4) + /* If jumps are cheap and the target does not support conditional + compare, turn some more codes into jumpy sequences. */ + else if (BRANCH_COST (optimize_insn_for_speed_p (), false) < 4 + && (targetm.gen_ccmp_first == NULL)) { if ((code2 == BIT_AND_EXPR && TYPE_PRECISION (TREE_TYPE (op0)) == 1 diff --git a/gcc/expmed.c b/gcc/expmed.c index e76b6fc..c8d63a9 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -5105,7 +5105,7 @@ expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target) } /* Helper function for emit_store_flag. */ -static rtx +rtx emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, enum machine_mode mode, enum machine_mode compare_mode, int unsignedp, rtx x, rtx y, int normalizep, diff --git a/gcc/expmed.h b/gcc/expmed.h index 4d01d1f..a567bad 100644 --- a/gcc/expmed.h +++ b/gcc/expmed.h @@ -20,6 +20,8 @@ along with GCC; see the file COPYING3. If not see #ifndef EXPMED_H #define EXPMED_H 1 +#include "insn-codes.h" + enum alg_code { alg_unknown, alg_zero, @@ -665,4 +667,9 @@ convert_cost (enum machine_mode to_mode, enum machine_mode from_mode, } extern int mult_by_coeff_cost (HOST_WIDE_INT, enum machine_mode, bool); + +extern rtx emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, + enum machine_mode mode, enum machine_mode compare_mode, + int unsignedp, rtx x, rtx y, int normalizep, + enum machine_mode target_mode); #endif diff --git a/gcc/expr.c b/gcc/expr.c index 512c024..04cf56e 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -146,8 +146,6 @@ static rtx store_field (rtx, HOST_WIDE_INT, HOST_WIDE_INT, static unsigned HOST_WIDE_INT highest_pow2_factor_for_target (const_tree, const_tree); static int is_aligning_offset (const_tree, const_tree); -static void expand_operands (tree, tree, rtx, rtx*, rtx*, - enum expand_modifier); static rtx reduce_to_bit_field_precision (rtx, rtx, tree); static rtx do_store_flag (sepops, rtx, enum machine_mode); #ifdef PUSH_ROUNDING @@ -7496,7 +7494,7 @@ convert_tree_comp_to_rtx (enum tree_code tcode, int unsignedp) The value may be stored in TARGET if TARGET is nonzero. The MODIFIER argument is as documented by expand_expr. */ -static void +void expand_operands (tree exp0, tree exp1, rtx target, rtx *op0, rtx *op1, enum expand_modifier modifier) { diff --git a/gcc/expr.h b/gcc/expr.h index 6a1d3ab..66ca82f 100644 --- a/gcc/expr.h +++ b/gcc/expr.h @@ -787,4 +787,6 @@ extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, by EXP. This does not include any offset in DECL_FIELD_BIT_OFFSET. */ extern tree component_ref_field_offset (tree); +extern void expand_operands (tree, tree, rtx, rtx*, rtx*, + enum expand_modifier); #endif /* GCC_EXPR_H */ diff --git a/gcc/optabs.c b/gcc/optabs.c index ca1c194..25aff1a 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -6453,7 +6453,7 @@ gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) /* Return rtx code for TCODE. Use UNSIGNEDP to select signed or unsigned operation code. */ -static enum rtx_code +enum rtx_code get_rtx_code (enum tree_code tcode, bool unsignedp) { enum rtx_code code; @@ -6503,6 +6503,12 @@ get_rtx_code (enum tree_code tcode, bool unsignedp) code = LTGT; break; + case BIT_AND_EXPR: + code = AND; + break; + case BIT_IOR_EXPR: + code = IOR; + break; default: gcc_unreachable (); } diff --git a/gcc/optabs.h b/gcc/optabs.h index 089b15a..61be4e2 100644 --- a/gcc/optabs.h +++ b/gcc/optabs.h @@ -91,6 +91,7 @@ extern rtx expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op, extern rtx expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, rtx op1, rtx op2, rtx target, int unsignedp); +extern enum rtx_code get_rtx_code (enum tree_code tcode, bool unsignedp); /* Expand a binary operation given optab and rtx operands. */