From patchwork Wed Mar 18 16:17:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yvan Roux X-Patchwork-Id: 45974 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f198.google.com (mail-lb0-f198.google.com [209.85.217.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A80432153B for ; Wed, 18 Mar 2015 16:17:28 +0000 (UTC) Received: by lbvn10 with SMTP id n10sf8240090lbv.1 for ; Wed, 18 Mar 2015 09:17:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:in-reply-to:references:date:message-id :subject:from:to:cc:content-type:x-original-sender :x-original-authentication-results; bh=4H8g1iUncHfIS8/PKvNsquvMeHubNoXonK1pSuH4tzU=; b=PD5OVn6kySDWrHR/IACEZv7XZXQHrVxPujxAX3+M2ybryC3wAzCuDabPfJtNgMbkW/ 3JwRVlaKQOZEbi9jH5HWA/8dASFmmOCxqG/B0Y3yYxdcsVJnOkRuJPrwiY45J2h0PAqF w+NuBXfIUNhvPBZ3ETCwUxCAkSk7O6MYfVn/epqVXgI171CL6cHAMb7RogMD1WYuxEg2 E+82rAbEtTckZLiRMp4tU06Av14AYcguDs7F/5Vzwgdgms21JntUmGaPb+EwK4x20Ksy SH0adzZgyKOAgvfxLEJuw9It4dTOhw/rhZgmUk8gXZXzZjDvLYKO0O8KpswJcysQPNSm Qgjg== X-Gm-Message-State: ALoCoQkeGljmzUVm9Vxc5YZG8QnMVFMfWcInNEdHQfZzdYjer8JlRkHyeTyhmjciKF2ETPovNLN/ X-Received: by 10.180.109.34 with SMTP id hp2mr924016wib.4.1426695447627; Wed, 18 Mar 2015 09:17:27 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.8.102 with SMTP id q6ls185265laa.24.gmail; Wed, 18 Mar 2015 09:17:27 -0700 (PDT) X-Received: by 10.112.92.66 with SMTP id ck2mr64608477lbb.105.1426695447131; Wed, 18 Mar 2015 09:17:27 -0700 (PDT) Received: from mail-la0-x229.google.com (mail-la0-x229.google.com. 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[209.132.180.131]) by mx.google.com with ESMTPS id y9si6492552pdj.185.2015.03.18.09.17.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Mar 2015 09:17:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-393716-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 104381 invoked by alias); 18 Mar 2015 16:17:05 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 104367 invoked by uid 89); 18 Mar 2015 16:17:05 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f170.google.com Received: from mail-ob0-f170.google.com (HELO mail-ob0-f170.google.com) (209.85.214.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 18 Mar 2015 16:17:02 +0000 Received: by obdfc2 with SMTP id fc2so35704029obd.3 for ; Wed, 18 Mar 2015 09:17:01 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.202.74.143 with SMTP id x137mr3847137oia.118.1426695421117; Wed, 18 Mar 2015 09:17:01 -0700 (PDT) Received: by 10.202.221.214 with HTTP; Wed, 18 Mar 2015 09:17:00 -0700 (PDT) In-Reply-To: References: <55095252.3000306@arm.com> Date: Wed, 18 Mar 2015 17:17:00 +0100 Message-ID: Subject: Re: [PATCH, ARM, PR64208] LRA ICE Fix From: Yvan Roux To: Kyrill Tkachov Cc: "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan , Richard Earnshaw , Vladimir Makarov X-IsSubscribed: yes X-Original-Sender: yvan.roux@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::229 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 18 March 2015 at 12:42, Yvan Roux wrote: > HI Kyrill, > > On 18 March 2015 at 11:24, Kyrill Tkachov wrote: >> Hi Yvan, >> >> >> On 18/03/15 10:19, Yvan Roux wrote: >>> >>> Hi, >>> >>> This is a fix for PR64208 where LRA loops when dealing with >>> iwmmxt_arm_movdi insn. As explain in the PR, the issue was introduced >>> on trunk and 4.9 branch by fix of PR rtl-optimization/60969 and then >>> workaround by r211798 (-fuse-caller-save enable for ARM). >>> >>> The changes in IRA cost made by PR60969, changed the register class of >>> this insn output from GENERAL_REGS to IWMMXT_REGS, and the >>> redundancies in the insn pattern alternatives description force LRA to >>> reload the pseudo, which generates the same iwmmxt_arm_movdi insn, >>> which can't be resolved, and so on ... >>> >>> Removing the redundancies fixes the issue, as LRA find that >>> alternative 8 (Uy => y) matches. >>> >>> This issue is present in 4.9 branch, but latent on trunk (the >>> clobbering of IP and CC information added during -fuse-caller-save >>> patch changed the register allocation). >>> >>> Cross compiled and regression tested on ARM targets (but not on an >>> IWMMXT one), is it ok for trunk and 4.9 branch ? >>> >>> Rq: I think that adding IP and CC clobbers to >>> CALL_INSN_FUNCTION_USAGE, as specified by AAPCS, in 4.9 branch is >>> something we need too, I've a patch for that if you agree on that. >>> >>> Thanks, >>> Yvan >>> >>> 2105-03-17 Yvan Roux >>> >>> PR target/64208 >>> * config/arm/iwmmxt.md ("*iwmmxt_arm_movdi"): Cleanup redundant >>> alternatives. >> >> >> As a general note, I think this patch should include the testcase from the >> PR. >> I can see that it's fairly self-contained. > > Yes, I wanted to find one that exhibits the issue on trunk as the PR > testcase doesn't, but don't find one so far. If it's fine to include > a testcase that don't fail without that patch on trunk, I can include > it. Here is the patch with the testcase. Cheers, Yvan gcc/ 2105-03-18 Yvan Roux PR target/64208 * config/arm/iwmmxt.md ("*iwmmxt_arm_movdi"): Cleanup redundant alternatives. gcc/testsuite/ 2105-03-18 Yvan Roux PR target/64208 * gcc.target/arm/pr64208.c: New test. diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index fda3c2c..d1a60ff 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -107,8 +107,8 @@ ) (define_insn "*iwmmxt_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,yr,y,yrUy,*w, r,*w,*w, *Uv") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,yr,y,yrUy,y, r,*w,*w,*Uvi,*w"))] + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))] "TARGET_REALLY_IWMMXT && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" diff --git a/gcc/testsuite/gcc.target/arm/pr64208.c b/gcc/testsuite/gcc.target/arm/pr64208.c new file mode 100644 index 0000000..96fd56d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr64208.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_iwmmxt_ok } */ +/* { dg-options "-O1 -mcpu=iwmmxt" } */ + +long long x6(void); +void x7(long long, long long); +void x8(long long); + +int x0; +long long *x1; + +void x2(void) { + long long *x3 = x1; + while (x1) { + long long x4 = x0, x5 = x6(); + x7(x4, x5); + x8(x5); + *x3 = 0; + } +}