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[209.132.180.131]) by mx.google.com with ESMTPS id dq10si19133111pdb.12.2015.05.04.02.14.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 May 2015 02:14:46 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-396760-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 110435 invoked by alias); 4 May 2015 09:14:14 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 109557 invoked by uid 89); 4 May 2015 09:14:13 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f171.google.com Received: from mail-wi0-f171.google.com (HELO mail-wi0-f171.google.com) (209.85.212.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 04 May 2015 09:14:12 +0000 Received: by wief7 with SMTP id f7so72958628wie.0 for ; Mon, 04 May 2015 02:14:09 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.180.216.40 with SMTP id on8mr18180188wic.55.1430730849371; Mon, 04 May 2015 02:14:09 -0700 (PDT) Received: by 10.28.4.204 with HTTP; Mon, 4 May 2015 02:14:09 -0700 (PDT) Date: Mon, 4 May 2015 11:14:09 +0200 Message-ID: Subject: [PATCH, ARM] Fix testcases that require Thumb2 effective target. From: Yvan Roux To: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Ramana Radhakrishnan , Kyrylo Tkachov X-IsSubscribed: yes X-Original-Sender: yvan.roux@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, This patch fixes two ARM testcases that require target to be Thumb2 effective. One is built for Cortex-m3, the purpose of the second one is to generate thumb2_addsi3_compare0_scratch insn and both are failing when compiled for armv5t for instance. Built and regtested, is it OK for trunk ? Thanks, Yvan 2015-05-04 Yvan Roux * gcc.target/arm/pr65067.c: Require Thumb2 effective target. * gcc.target/arm/pr65924.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/pr65067.c b/gcc/testsuite/gcc.target/arm/pr65067.c index 9ddd7bb..05da294 100644 --- a/gcc/testsuite/gcc.target/arm/pr65067.c +++ b/gcc/testsuite/gcc.target/arm/pr65067.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-options "-mthumb -mcpu=cortex-m3 -O2" } */ struct tmp { diff --git a/gcc/testsuite/gcc.target/arm/pr65924.c b/gcc/testsuite/gcc.target/arm/pr65924.c index 746749f..e1ad394 100644 --- a/gcc/testsuite/gcc.target/arm/pr65924.c +++ b/gcc/testsuite/gcc.target/arm/pr65924.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-options "-O2 -mthumb" } */ int a, b, c;