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[209.132.180.131]) by mx.google.com with ESMTPS id j73si1293729pgc.736.2017.11.27.09.03.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Nov 2017 09:03:57 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-467971-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=GDxFE4Sk; spf=pass (google.com: domain of gcc-patches-return-467971-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-467971-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=cwtFfGgUcz0427t7Ihfsae4b3kErrMe4b9rzaxI655A IvakxtP2IwKl0Fil2JLSnNNcIMR+x1mjbhnZY2OX+IY6Rhx1tohqarHj7oGX7n+Z bUo+z+0Aezg5ixFPiFSF8S/kBiNjtsItTGUhcMNKALyEiAoy6E58AuoMkSSt5Wfg = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=PgK7AdIvn5OXg90HED3TByqaj2s=; b=GDxFE4Sk31RsI93eY Abmvb+8AnGr3P81O3o3d3gcMRezyx3OtqlqX8QG56a8lq5uoKywr4ieZLk/LqlXk +Kg2aFcNvHtiN+K05fLlh5I1lSbZSHlZU9KJrFZxwSf4k/lV6GESvIqBRUoNRzOu a8YnfpzEtrulEB2jZe2xr16gj8= Received: (qmail 83702 invoked by alias); 27 Nov 2017 17:03:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 83470 invoked by uid 89); 27 Nov 2017 17:03:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=d*, rework, 2429 X-HELO: mail-yb0-f177.google.com Received: from mail-yb0-f177.google.com (HELO mail-yb0-f177.google.com) (209.85.213.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 27 Nov 2017 17:03:35 +0000 Received: by mail-yb0-f177.google.com with SMTP id v77so3793946ybi.5 for ; Mon, 27 Nov 2017 09:03:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=AwzFUD17uCY2Nb2yWXM0sVPtNtV6EZffsnrrkXsmSa0=; b=gv/q/9G6zU2y9UwylRQBw6ZMoC9OCiYrgaU0It5zsl+9UG+afpKRKsx8BQr9+hzCyw jK2eSgYRMWeDJfcZ9SV92Xw8wuvKs1O5Cyc3TWpjS6KdBjFHywxlrUuvENqusMUstnvS SkTUmCvkES1TuNjwRJNaqgzG2qSmihypzk37SmWpqq0jmveNGSJdgxAAUzwA6DTuGd1y 8365z1ZzMFwtUCbg1NyqY2ltyw9joeXbUw+UzM6kTAmMWmE4Nt7FYhgSBJzMNtNLh2RO SZdg2F3f+MHwXcxiRpm9QXfTRpRVy+rjt0Q9qWhIQMue3OoxOYoAun81P2dDKdXaW1KY n59Q== X-Gm-Message-State: AJaThX4m6KTjtD8m6PvK/9wy7ypbuzGmeobULToArt4BJzeN3ibjCw4z 4D2HEkPM52h3hKpZwT3kNP/h1Yg58pe8WZhoN7QjIgQ1BYQ= X-Received: by 10.37.188.210 with SMTP id l18mr25191163ybm.52.1511802213385; Mon, 27 Nov 2017 09:03:33 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.182.1 with HTTP; Mon, 27 Nov 2017 09:03:32 -0800 (PST) From: Charles Baylis Date: Mon, 27 Nov 2017 17:03:32 +0000 Message-ID: Subject: [PATCH] ARM testsuite: force hardfp for addr-modes-float.c To: GCC Patches , Kyrill Tkachov , Richard Earnshaw , Ramana Radhakrishnan , nickc@redhat.com Cc: Christophe Lyon X-IsSubscribed: yes Some of the new tests in addr-modes-float.c, which were introduced for the rework of addressing modes costs [1] fail when GCC is configured to default to a softfp calling convention. Fix this by annotating the test functions with __attribute__((pcs("aapcs-vfp"))). Thanks to Christophe for pointing this out. [1] https://gcc.gnu.org/ml/gcc-patches/2017-11/msg02149.html Charles Baylis * gcc.target/arm/addr-modes-float.c (ATTR): New define. (POST_STORE): Pass ATTR as 2nd argument. (POST_LOAD): Likewise. (POST_STORE_VEC): Likewise. * gcc.target/arm/addr-modes-int.c (ATTR): New define. (PRE_STORE): Pass ATTR as 2nd argument. (POST_STORE): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. * gcc.target/arm/addr-modes.h (PRE_STORE): New parameter. (POST_STORE): Likewise. (POST_STORE_VEC): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. (POST_LOAD_VEC): Likewise. >From c8743026e53429131e6677aaca7b0840ecc11e25 Mon Sep 17 00:00:00 2001 From: Charles Baylis Date: Fri, 24 Nov 2017 16:24:18 +0000 Subject: [PATCH] [ARM] testsuite: force hardfp in addr-modes-float.c gcc/testsuite/ChangeLog: Charles Baylis * gcc.target/arm/addr-modes-float.c (ATTR): New define. (POST_STORE): Pass ATTR as 2nd argument. (POST_LOAD): Likewise. (POST_STORE_VEC): Likewise. * gcc.target/arm/addr-modes-int.c (ATTR): New define. (PRE_STORE): Pass ATTR as 2nd argument. (POST_STORE): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. * gcc.target/arm/addr-modes.h (PRE_STORE): New parameter. (POST_STORE): Likewise. (POST_STORE_VEC): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. (POST_LOAD_VEC): Likewise. Change-Id: I7f85e811194098da8f1b7d243653d7873f132fff --- gcc/testsuite/gcc.target/arm/addr-modes-float.c | 26 +++++++++--------- gcc/testsuite/gcc.target/arm/addr-modes-int.c | 35 ++++++++++++++----------- gcc/testsuite/gcc.target/arm/addr-modes.h | 30 ++++++++++----------- 3 files changed, 48 insertions(+), 43 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-float.c b/gcc/testsuite/gcc.target/arm/addr-modes-float.c index 3b4235c..300a2bea 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes-float.c +++ b/gcc/testsuite/gcc.target/arm/addr-modes-float.c @@ -7,35 +7,37 @@ #include "addr-modes.h" -POST_STORE(float) +#define ATTR __attribute__((__pcs__("aapcs-vfp"))) + +POST_STORE(float, ATTR) /* { dg-final { scan-assembler "vstmia.32" } } */ -POST_STORE(double) +POST_STORE(double, ATTR) /* { dg-final { scan-assembler "vstmia.64" } } */ -POST_LOAD(float) +POST_LOAD(float, ATTR) /* { dg-final { scan-assembler "vldmia.32" } } */ -POST_LOAD(double) +POST_LOAD(double, ATTR) /* { dg-final { scan-assembler "vldmia.64" } } */ -POST_STORE_VEC (int8_t, int8x8_t, vst1_s8) +POST_STORE_VEC (int8_t, int8x8_t, vst1_s8, ATTR) /* { dg-final { scan-assembler "vst1.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8) +POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8, ATTR) /* { dg-final { scan-assembler "vst1.8\t\{.*\[-,\]d.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8) +POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8, ATTR) /* { dg-final { scan-assembler "vst2.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8) +POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8, ATTR) /* { dg-final { scan-assembler "vst2.8\t\{.*-d.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8) +POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8, ATTR) /* { dg-final { scan-assembler "vst3.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8) +POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8, ATTR) /* { dg-final { scan-assembler "vst3.8\t\{d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vst3.8\t\{d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ -POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8) +POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8, ATTR) /* { dg-final { scan-assembler "vst4.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8) +POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8, ATTR) /* { dg-final { scan-assembler "vst4.8\t\{d\[02468\], d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vst4.8\t\{d\[13579\], d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-int.c b/gcc/testsuite/gcc.target/arm/addr-modes-int.c index e3e1e6a..90b7425 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes-int.c +++ b/gcc/testsuite/gcc.target/arm/addr-modes-int.c @@ -7,40 +7,43 @@ typedef long long ll; -PRE_STORE(char) +/* no special function attribute required */ +#define ATTR /* */ + +PRE_STORE(char, ATTR) /* { dg-final { scan-assembler "strb.*#1]!" } } */ -PRE_STORE(short) +PRE_STORE(short, ATTR) /* { dg-final { scan-assembler "strh.*#2]!" } } */ -PRE_STORE(int) +PRE_STORE(int, ATTR) /* { dg-final { scan-assembler "str.*#4]!" } } */ -PRE_STORE(ll) +PRE_STORE(ll, ATTR) /* { dg-final { scan-assembler "strd.*#8]!" } } */ -POST_STORE(char) +POST_STORE(char, ATTR) /* { dg-final { scan-assembler "strb.*], #1" } } */ -POST_STORE(short) +POST_STORE(short, ATTR) /* { dg-final { scan-assembler "strh.*], #2" } } */ -POST_STORE(int) +POST_STORE(int, ATTR) /* { dg-final { scan-assembler "str.*], #4" } } */ -POST_STORE(ll) +POST_STORE(ll, ATTR) /* { dg-final { scan-assembler "strd.*], #8" } } */ -PRE_LOAD(char) +PRE_LOAD(char, ATTR) /* { dg-final { scan-assembler "ldrb.*#1]!" } } */ -PRE_LOAD(short) +PRE_LOAD(short, ATTR) /* { dg-final { scan-assembler "ldrsh.*#2]!" } } */ -PRE_LOAD(int) +PRE_LOAD(int, ATTR) /* { dg-final { scan-assembler "ldr.*#4]!" } } */ -PRE_LOAD(ll) +PRE_LOAD(ll, ATTR) /* { dg-final { scan-assembler "ldrd.*#8]!" } } */ -POST_LOAD(char) +POST_LOAD(char, ATTR) /* { dg-final { scan-assembler "ldrb.*], #1" } } */ -POST_LOAD(short) +POST_LOAD(short, ATTR) /* { dg-final { scan-assembler "ldrsh.*], #2" } } */ -POST_LOAD(int) +POST_LOAD(int, ATTR) /* { dg-final { scan-assembler "ldr.*], #4" } } */ -POST_LOAD(ll) +POST_LOAD(ll, ATTR) /* { dg-final { scan-assembler "ldrd.*], #8" } } */ /* { dg-final { scan-assembler-not "\tadd" } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes.h b/gcc/testsuite/gcc.target/arm/addr-modes.h index eac4678..9844c6a 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes.h +++ b/gcc/testsuite/gcc.target/arm/addr-modes.h @@ -1,22 +1,22 @@ -#define PRE_STORE(T) \ - T * \ +#define PRE_STORE(T, ATTR) \ + ATTR T * \ T ## _pre_store (T *p, T v) \ { \ *++p = v; \ return p; \ } \ -#define POST_STORE(T) \ - T * \ +#define POST_STORE(T, ATTR) \ + ATTR T * \ T ## _post_store (T *p, T v) \ { \ *p++ = v; \ return p; \ } -#define POST_STORE_VEC(T, VT, OP) \ - T * \ +#define POST_STORE_VEC(T, VT, OP, ATTR) \ + ATTR T * \ VT ## _post_store (T * p, VT v) \ { \ OP (p, v); \ @@ -24,29 +24,29 @@ return p; \ } -#define PRE_LOAD(T) \ - void \ +#define PRE_LOAD(T, ATTR) \ + ATTR void \ T ## _pre_load (T *p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ T x = *++p; \ f ## T (p, x); \ } -#define POST_LOAD(T) \ - void \ +#define POST_LOAD(T, ATTR) \ + ATTR void \ T ## _post_load (T *p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ T x = *p++; \ f ## T (p, x); \ } -#define POST_LOAD_VEC(T, VT, OP) \ - void \ +#define POST_LOAD_VEC(T, VT, OP, ATTR) \ + ATTR void \ VT ## _post_load (T * p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ VT x = OP (p, v); \ p += sizeof (VT) / sizeof (T); \ f ## T (p, x); \ -- 2.7.4