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[209.132.180.131]) by mx.google.com with ESMTPS id bu1si1230759pbb.225.2015.01.20.07.31.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Jan 2015 07:31:04 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-390013-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 19964 invoked by alias); 20 Jan 2015 15:30:47 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19761 invoked by uid 89); 20 Jan 2015 15:30:45 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qg0-f54.google.com Received: from mail-qg0-f54.google.com (HELO mail-qg0-f54.google.com) (209.85.192.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 20 Jan 2015 15:30:41 +0000 Received: by mail-qg0-f54.google.com with SMTP id q108so3330680qgd.13 for ; Tue, 20 Jan 2015 07:30:38 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.224.36.199 with SMTP id u7mr37633242qad.72.1421767838712; Tue, 20 Jan 2015 07:30:38 -0800 (PST) Received: by 10.140.84.176 with HTTP; Tue, 20 Jan 2015 07:30:38 -0800 (PST) In-Reply-To: References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-18-git-send-email-christophe.lyon@linaro.org> <54B94FF3.4010601@arm.com> Date: Tue, 20 Jan 2015 16:30:38 +0100 Message-ID: Subject: Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests. From: Christophe Lyon To: Tejas Belagod Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22e as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 16 January 2015 at 18:54, Christophe Lyon wrote: > On 16 January 2015 at 18:52, Tejas Belagod wrote: >> On 13/01/15 15:18, Christophe Lyon wrote: >>> >>> * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file. >>> >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc >>> new file mode 100644 >>> index 0000000..7ac2ed4 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc >>> @@ -0,0 +1,67 @@ >>> +#define FNNAME1(NAME) exec_ ## NAME >>> +#define FNNAME(NAME) FNNAME1(NAME) >>> + >>> +void FNNAME (INSN_NAME) (void) >>> +{ >>> + /* Basic test: y=OP(x), then store the result. */ >>> +#define TEST_VPADD1(INSN, T1, T2, W, N) >>> \ >>> + VECT_VAR(vector_res, T1, W, N) = \ >>> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \ >>> + VECT_VAR(vector, T1, W, N)); \ >>> + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \ >>> + VECT_VAR(vector_res, T1, W, N)) >>> + >>> +#define TEST_VPADD(INSN, T1, T2, W, N) \ >>> + TEST_VPADD1(INSN, T1, T2, W, N) \ >>> + >>> + /* No need for 64 bits variants. */ >>> + DECL_VARIABLE(vector, int, 8, 8); >>> + DECL_VARIABLE(vector, int, 16, 4); >>> + DECL_VARIABLE(vector, int, 32, 2); >>> + DECL_VARIABLE(vector, uint, 8, 8); >>> + DECL_VARIABLE(vector, uint, 16, 4); >>> + DECL_VARIABLE(vector, uint, 32, 2); >>> + DECL_VARIABLE(vector, float, 32, 2); >>> + >>> + DECL_VARIABLE(vector_res, int, 8, 8); >>> + DECL_VARIABLE(vector_res, int, 16, 4); >>> + DECL_VARIABLE(vector_res, int, 32, 2); >>> + DECL_VARIABLE(vector_res, uint, 8, 8); >>> + DECL_VARIABLE(vector_res, uint, 16, 4); >>> + DECL_VARIABLE(vector_res, uint, 32, 2); >>> + DECL_VARIABLE(vector_res, float, 32, 2); >>> + >>> + clean_results (); >>> + >>> + /* Initialize input "vector" from "buffer". */ >>> + VLOAD(vector, buffer, , int, s, 8, 8); >>> + VLOAD(vector, buffer, , int, s, 16, 4); >>> + VLOAD(vector, buffer, , int, s, 32, 2); >>> + VLOAD(vector, buffer, , uint, u, 8, 8); >>> + VLOAD(vector, buffer, , uint, u, 16, 4); >>> + VLOAD(vector, buffer, , uint, u, 32, 2); >>> + VLOAD(vector, buffer, , float, f, 32, 2); >>> + >>> + /* Apply a unary operator named INSN_NAME. */ >> >> >> Unary op? >> > Hmm cut & paste issue. Thanks > Here is an updated versoin, also renaming VPADD into VPXXX, since it's in a template. >> >>> + TEST_VPADD(INSN_NAME, int, s, 8, 8); >>> + TEST_VPADD(INSN_NAME, int, s, 16, 4); >>> + TEST_VPADD(INSN_NAME, int, s, 32, 2); >>> + TEST_VPADD(INSN_NAME, uint, u, 8, 8); >>> + TEST_VPADD(INSN_NAME, uint, u, 16, 4); >>> + TEST_VPADD(INSN_NAME, uint, u, 32, 2); >>> + TEST_VPADD(INSN_NAME, float, f, 32, 2); >>> + >>> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, ""); >>> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, ""); >>> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); >>> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, ""); >>> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, ""); >>> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); >>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); >>> +} >>> + >>> +int main (void) >>> +{ >>> + FNNAME (INSN_NAME) (); >>> + return 0; >>> +} >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c >>> new file mode 100644 >>> index 0000000..5ddfd3d >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c >>> @@ -0,0 +1,19 @@ >>> +#include >>> +#include "arm-neon-ref.h" >>> +#include "compute-ref-data.h" >>> + >>> +#define INSN_NAME vpadd >>> +#define TEST_MSG "VPADD" >>> + >>> +/* Expected results. */ >>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed, >>> + 0xe1, 0xe5, 0xe9, 0xed }; >>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 }; >>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 }; >>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed, >>> + 0xe1, 0xe5, 0xe9, 0xed }; >>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 >>> }; >>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 }; >>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 }; >>> + >>> +#include "vpXXX.inc" >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c >>> new file mode 100644 >>> index 0000000..f27a9a9 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c >>> @@ -0,0 +1,20 @@ >>> +#include >>> +#include "arm-neon-ref.h" >>> +#include "compute-ref-data.h" >>> + >>> + >>> +#define INSN_NAME vpmax >>> +#define TEST_MSG "VPMAX" >>> + >>> +/* Expected results. */ >>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, >>> + 0xf1, 0xf3, 0xf5, 0xf7 }; >>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 }; >>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 }; >>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, >>> + 0xf1, 0xf3, 0xf5, 0xf7 }; >>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 >>> }; >>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 }; >>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 }; >>> + >>> +#include "vpXXX.inc" >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c >>> new file mode 100644 >>> index 0000000..a7cb696 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c >>> @@ -0,0 +1,20 @@ >>> +#include >>> +#include "arm-neon-ref.h" >>> +#include "compute-ref-data.h" >>> + >>> + >>> +#define INSN_NAME vpmin >>> +#define TEST_MSG "VPMIN" >>> + >>> +/* Expected results. */ >>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6, >>> + 0xf0, 0xf2, 0xf4, 0xf6 }; >>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 }; >>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; >>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6, >>> + 0xf0, 0xf2, 0xf4, 0xf6 }; >>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 >>> }; >>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 }; >>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 }; >>> + >>> +#include "vpXXX.inc" >>> >> >> Otherwise LGTM. >> >> Tejas. >> >From 3a8d5a974d49332cd4de6675aa0d58501b967518 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 9 Dec 2014 22:27:01 +0100 Subject: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc new file mode 100644 index 0000000..c1b7235 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc @@ -0,0 +1,67 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: y=OP(x), then store the result. */ +#define TEST_VPXXX1(INSN, T1, T2, W, N) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector, T1, W, N)); \ + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)) + +#define TEST_VPXXX(INSN, T1, T2, W, N) \ + TEST_VPXXX1(INSN, T1, T2, W, N) \ + + /* No need for 64 bits variants. */ + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, uint, 8, 8); + DECL_VARIABLE(vector, uint, 16, 4); + DECL_VARIABLE(vector, uint, 32, 2); + DECL_VARIABLE(vector, float, 32, 2); + + DECL_VARIABLE(vector_res, int, 8, 8); + DECL_VARIABLE(vector_res, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 2); + DECL_VARIABLE(vector_res, uint, 8, 8); + DECL_VARIABLE(vector_res, uint, 16, 4); + DECL_VARIABLE(vector_res, uint, 32, 2); + DECL_VARIABLE(vector_res, float, 32, 2); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + VLOAD(vector, buffer, , int, s, 8, 8); + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, , uint, u, 8, 8); + VLOAD(vector, buffer, , uint, u, 16, 4); + VLOAD(vector, buffer, , uint, u, 32, 2); + VLOAD(vector, buffer, , float, f, 32, 2); + + /* Apply a binary operator named INSN_NAME. */ + TEST_VPXXX(INSN_NAME, int, s, 8, 8); + TEST_VPXXX(INSN_NAME, int, s, 16, 4); + TEST_VPXXX(INSN_NAME, int, s, 32, 2); + TEST_VPXXX(INSN_NAME, uint, u, 8, 8); + TEST_VPXXX(INSN_NAME, uint, u, 16, 4); + TEST_VPXXX(INSN_NAME, uint, u, 32, 2); + TEST_VPXXX(INSN_NAME, float, f, 32, 2); + + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c new file mode 100644 index 0000000..5ddfd3d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c @@ -0,0 +1,19 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vpadd +#define TEST_MSG "VPADD" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed, + 0xe1, 0xe5, 0xe9, 0xed }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed, + 0xe1, 0xe5, 0xe9, 0xed }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 }; + +#include "vpXXX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c new file mode 100644 index 0000000..f27a9a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c @@ -0,0 +1,20 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + + +#define INSN_NAME vpmax +#define TEST_MSG "VPMAX" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, + 0xf1, 0xf3, 0xf5, 0xf7 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, + 0xf1, 0xf3, 0xf5, 0xf7 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 }; + +#include "vpXXX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c new file mode 100644 index 0000000..a7cb696 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c @@ -0,0 +1,20 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + + +#define INSN_NAME vpmin +#define TEST_MSG "VPMIN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6, + 0xf0, 0xf2, 0xf4, 0xf6 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6, + 0xf0, 0xf2, 0xf4, 0xf6 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 }; + +#include "vpXXX.inc" -- 2.1.0