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[209.132.180.131]) by mx.google.com with ESMTPS id p14si2718159pli.295.2017.12.08.02.56.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 02:56:51 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468759-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Kt51J2ef; spf=pass (google.com: domain of gcc-patches-return-468759-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468759-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=AeUikLlsSsTCVRurVHZDF4zDvs3DudH+fuzI0ZfBQ7U/ReccA5 126vCy6ismGRDJYGSlPDko2OfoLqGF43iD7RpoYD4YZzNoDMPHS2Wu9WPmFRw5xX jx+yNfZ/tHGLATh7b7uxD/XJ3WlA1nqu/WA1mHl1mXmC0/blAne84V/Po= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=C6vDshw+QsCHsE1WzDE15glsbcw=; b=Kt51J2efUrOE8XxiVXZJ 8bIwiqHNUn1a36ut1njQT5SjYbNd9LEyh81+/R1+I763BQtS61KTH3jXcC59ipHe hiei1SrsG8vU6H6M1OvnGa7vDqT6cdHRXfb8VSieqpfZ0Gdbri/Eief2bh+1lHH+ 7QAY09qkdS0Y/l4VBWkWLiA= Received: (qmail 128966 invoked by alias); 8 Dec 2017 10:56:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 128951 invoked by uid 89); 8 Dec 2017 10:56:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=HX-Envelope-From:sk:Richard, handwritten, hand-written, understanding X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 08 Dec 2017 10:56:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0385E1529; Fri, 8 Dec 2017 02:56:36 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 823513F24A; Fri, 8 Dec 2017 02:56:35 -0800 (PST) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: [arm] Generate a -mfpu= option for passing to the assembler Message-ID: Date: Fri, 8 Dec 2017 10:56:33 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 When gcc runs with the new -mfpu=auto option (either explicitly or when that's the default behaviour) then this option is not passed through to the assembler as we cannot rely on the assembler understanding it (currently it doesn't understand it at all, but in future that might change). That means that the assembler falls back to its builtin default, which may not correspond to what the user expected based on the command-line options they passed. Normally that wouldn't matter because assembler files generated by the compiler will contain explicit directives that set the FPU type directly and override any internal defaults; but when the compiler driver is used to invoke the assembler directly (because the source file ends in .s or .S) then this might cause a problem if that assumes the FPU matches the compiler. To address this, this patch makes the driver construct a -mfpu= option for the assembler in the same way as the compiler generates an internal .fpu directive. As mentioned, this makes no difference if the assembler file explicitly overrides the command line options, but helps in the case where this is implicit. 2017-06-08 Richard Earnshaw * config/arm/arm.h (arm_asm_auto_mfpu): Declare. (ASM_CPU_SPEC_FUNCTIONS): Add new rule asm_auto_mfpu. (ASM_CPU_SPEC): Use it if -mfpu is set to auto. * common/config/arm/arm-common.c (arm_asm_auto_mfpu): New function. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 5ae20fe..90b04f1 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -823,6 +823,86 @@ arm_be8_option (int argc, const char **argv) return ""; } +/* Generate a -mfpu= option for passing to the assembler. This is + only called when -mfpu was set (possibly defaulted) to auto and is + needed to ensure that the assembler knows the correct FPU to use. + It wouldn't really be needed except that the compiler can be used + to invoke the assembler directly on hand-written files that lack + the necessary internal .fpu directives. We assume that the architecture + canonicalization calls have already been made so that we have a final + -march= option to derive the fpu from. */ +const char* +arm_asm_auto_mfpu (int argc, const char **argv) +{ + static char *auto_fpu = NULL; + const char *arch = NULL; + static const enum isa_feature fpu_bitlist[] + = { ISA_ALL_FPU_INTERNAL, isa_nobit }; + const arch_option *selected_arch; + static const char* fpuname = "softvfp"; + + /* Handle multiple calls to this routine. */ + if (auto_fpu) + { + free (auto_fpu); + auto_fpu = NULL; + } + + while (argc) + { + if (strcmp (argv[0], "arch") == 0) + arch = argv[1]; + else + fatal_error (input_location, + "unrecognized operand to %%:asm_auto_mfpu"); + argc -= 2; + argv += 2; + } + + auto_sbitmap target_isa (isa_num_bits); + auto_sbitmap fpubits (isa_num_bits); + + gcc_assert (arch != NULL); + selected_arch = arm_parse_arch_option_name (all_architectures, + "-march", arch); + if (selected_arch == NULL) + return ""; + + arm_initialize_isa (target_isa, selected_arch->common.isa_bits); + arm_parse_option_features (target_isa, &selected_arch->common, + strchr (arch, '+')); + arm_initialize_isa (fpubits, fpu_bitlist); + + bitmap_and (fpubits, fpubits, target_isa); + + /* The logic below is essentially identical to that in + arm.c:arm_identify_fpu_from_isa(), but that only works in the main + part of the compiler. */ + + /* If there are no FPU capability bits, we just pass -mfpu=softvfp. */ + if (!bitmap_empty_p (fpubits)) + { + unsigned int i; + auto_sbitmap cand_fpubits (isa_num_bits); + for (i = 0; i < TARGET_FPU_auto; i++) + { + arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits); + if (bitmap_equal_p (fpubits, cand_fpubits)) + { + fpuname = all_fpus[i].name; + break; + } + } + + gcc_assert (i != TARGET_FPU_auto); + } + + auto_fpu = (char *) xmalloc (strlen (fpuname) + sizeof ("-mfpu=")); + strcpy (auto_fpu, "-mfpu="); + strcat (auto_fpu, fpuname); + return auto_fpu; +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index b189951..ac51412 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2166,13 +2166,16 @@ extern int making_const_table; extern const char *arm_rewrite_mcpu (int argc, const char **argv); extern const char *arm_rewrite_march (int argc, const char **argv); +extern const char *arm_asm_auto_mfpu (int argc, const char **argv); #define ASM_CPU_SPEC_FUNCTIONS \ { "rewrite_mcpu", arm_rewrite_mcpu }, \ - { "rewrite_march", arm_rewrite_march }, + { "rewrite_march", arm_rewrite_march }, \ + { "asm_auto_mfpu", arm_asm_auto_mfpu }, #define ASM_CPU_SPEC \ + " %{mfpu=auto:%