From patchwork Wed Jan 17 14:55:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 124809 Delivered-To: patch@linaro.org Received: by 10.46.62.1 with SMTP id l1csp70916lja; Wed, 17 Jan 2018 06:56:47 -0800 (PST) X-Google-Smtp-Source: ACJfBovrEXi1qajoz0/MVao0abPFqX4H7oPKUiuCsYhddFO7mpvDUcFMdVpamWtab4aliRHMyGEr X-Received: by 10.99.163.2 with SMTP id s2mr5590056pge.264.1516201007083; Wed, 17 Jan 2018 06:56:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516201007; cv=none; d=google.com; s=arc-20160816; b=Vk/xcnwZ4LtHgLxY3VrQbtbOrKeuFzJcn37GUnEwWuH1nJc1nPY1FxOudWADmFG0li 9EzWBCR5t49TV3aQJrMHt8FeOcmyvfwyPTl4cMRTv2U2BdKBCoif63XIEUALqcYd8z7D cjq68FA5hAUwUKttnTQpNChntp+5z+Er4K/vK1uQh3+KXmD7557oy7GV6xyXG3caque6 hjyr4LMStiNJJzDnOcUiSJVbKIdLh8bg48mezLdCCwHa4jezRArw/RERfPxkQRUj4wgU q9G0VWPChJP5MYdDf/2aNWpVpzs7HQPy53dWm9DYxZJg9rQEmjboSJu8g/oUG90JzwKb QdoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:references:in-reply-to :message-id:date:subject:cc:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=WcOyiktWBnz5Sp3F/vB41+7HLiiVxXE7r80Wxiw6JuA=; b=eVQyrMqrMvcUoIoHKeoUD4lukfTK+27DEFIZN4PFByCpx3rR/OpJEZ/u62a+bGKVcz lw/FaZUZ2tPLXq5nhlGDo9NgreZaPNgtwdz/JA0XGmTsEomRZL2ci3ccPwTGT3DqZdX5 bjpKUBHBprHflZc/+dmP+e648rhppc1FM2SQEoB+oW5JDTZEmYg+ncT8VUofHVuwJLYB fxlh1Y9Tg+23qbNEl3ZMjIjJGXw8lm049fbgVuHng3AXbyjLui2jvXS0wblWRMn+n+3G /UnhcpdgXL1Eob1Ey7DnsHaS6vEXPLQGaL+vjdLyNvgwGP1a1PJsRa5cjKwkhozCjzs3 NqIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=a90iOO4k; spf=pass (google.com: domain of gcc-patches-return-471478-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-471478-patch=linaro.org@gcc.gnu.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id c4si4008575pgt.44.2018.01.17.06.56.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jan 2018 06:56:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-471478-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=a90iOO4k; spf=pass (google.com: domain of gcc-patches-return-471478-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-471478-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=ucU+c8gGqoOzk63fU2ahsKnKaTG+N2sjcIXdYQwJabnHiUvCoZT0Z ICiHWdbRntmECcFLbUCJ0HRh+owzk5e1aQC8jNhmUuEhURZ4X3tBSp3vHFGTzOAJ 7YeUBqbY2KIpxtZKxXox3rNN2Fj5jWVPXvG0tKa3Dn3d1AvZGQlAiU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=ggsJhnA0pQA2WMvZWYtsx/CfacA=; b=a90iOO4kDrG3dfiQC0/sd3Hz+gdA fGf/DZXM30vgRSZ8PmRrEyhbJ5xbN/w7t+e1ut8uN8mzN3aWTnhJfBXdrvPgTar9 obJ1M/gapHCtsL5m8cSK2gm+Gkik0pXXhBkyCKmEMx2VGUmWMvmQEVb5dQdScwvV +g2rkMLJyEI/3ts= Received: (qmail 84990 invoked by alias); 17 Jan 2018 14:56:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 84866 invoked by uid 89); 17 Jan 2018 14:56:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=multimedia, Multimedia, wireless, llr X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 17 Jan 2018 14:56:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D69AF1610; Wed, 17 Jan 2018 06:56:09 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A7CC3F557; Wed, 17 Jan 2018 06:56:08 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 3/3] [arm] Implement support for the de-speculation intrinsic Date: Wed, 17 Jan 2018 14:55:36 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 This patch implements despeculation on ARM. We only support it when generating ARM or Thumb2 code (we need conditional execution); and we only support it for sizes up to DImode. For unsupported cases we fall back to the generic code generation sequence so that a suitable failure warning is emitted. * config/arm/arm.c (arm_speculation_safe_load): New function (TARGET_SPECULATION_SAFE_LOAD): Redefine. * config/arm/unspec.md (VUNSPEC_NOSPECULATE): New unspec_volatile code. * config/arm/arm.md (cmp_ior): Make this pattern callable. (nospeculate, nospeculatedi): New patterns. --- gcc/config/arm/arm.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++ gcc/config/arm/arm.md | 40 ++++++++++++++++++- gcc/config/arm/unspecs.md | 1 + 3 files changed, 140 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 11e35ad..f28ad2b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -321,6 +321,8 @@ static unsigned int arm_hard_regno_nregs (unsigned int, machine_mode); static bool arm_hard_regno_mode_ok (unsigned int, machine_mode); static bool arm_modes_tieable_p (machine_mode, machine_mode); static HOST_WIDE_INT arm_constant_alignment (const_tree, HOST_WIDE_INT); +static rtx arm_speculation_safe_load (machine_mode, rtx, rtx, rtx, rtx, rtx, + bool); /* Table of machine attributes. */ static const struct attribute_spec arm_attribute_table[] = @@ -804,6 +806,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CONSTANT_ALIGNMENT #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment + +#undef TARGET_SPECULATION_SAFE_LOAD +#define TARGET_SPECULATION_SAFE_LOAD arm_speculation_safe_load /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; @@ -31523,6 +31528,101 @@ arm_constant_alignment (const_tree exp, HOST_WIDE_INT align) return align; } +static rtx +arm_speculation_safe_load (machine_mode mode, rtx result, rtx mem, + rtx lower_bound, rtx upper_bound, + rtx cmpptr, bool warn) +{ + rtx cond, comparison; + + /* We can't support this for Thumb1 as we have no suitable conditional + move operations. Nor do we support it for TImode. For both + these cases fall back to the generic code sequence which will emit + a suitable warning for us. */ + if (mode == TImode || TARGET_THUMB1) + return default_speculation_safe_load (mode, result, mem, lower_bound, + upper_bound, cmpptr, warn); + + + rtx target = gen_reg_rtx (mode); + rtx tgt2 = result; + + if (!register_operand (tgt2, mode)) + tgt2 = gen_reg_rtx (mode); + + if (!register_operand (cmpptr, ptr_mode)) + cmpptr = force_reg (ptr_mode, cmpptr); + + /* There's no point in comparing against a lower bound that is NULL, all + addresses are greater than or equal to that. */ + if (lower_bound == const0_rtx) + { + if (!register_operand (upper_bound, ptr_mode)) + upper_bound = force_reg (ptr_mode, upper_bound); + + cond = arm_gen_compare_reg (GEU, cmpptr, upper_bound, NULL); + comparison = gen_rtx_GEU (VOIDmode, cond, const0_rtx); + } + else + { + /* We want to generate code for + result = (cmpptr < lower || cmpptr >= upper) ? 0 : *ptr; + Which can be recast to + result = (cmpptr < lower || upper <= cmpptr) ? 0 : *ptr; + which can be implemented as + cmp cmpptr, lower + cmpcs upper, cmpptr + bls 1f + ldr result, [ptr] + 1: + movls result, #0 + with suitable IT instructions as needed for thumb2. Later + optimization passes may make the load conditional. */ + + if (!register_operand (lower_bound, ptr_mode)) + lower_bound = force_reg (ptr_mode, lower_bound); + + if (!register_operand (upper_bound, ptr_mode)) + upper_bound = force_reg (ptr_mode, upper_bound); + + rtx comparison1 = gen_rtx_LTU (SImode, cmpptr, lower_bound); + rtx comparison2 = gen_rtx_LEU (SImode, upper_bound, cmpptr); + cond = gen_rtx_REG (arm_select_dominance_cc_mode (comparison1, + comparison2, + DOM_CC_X_OR_Y), + CC_REGNUM); + emit_insn (gen_cmp_ior (cmpptr, lower_bound, upper_bound, cmpptr, + comparison1, comparison2, cond)); + comparison = gen_rtx_NE (SImode, cond, const0_rtx); + } + + rtx_code_label *label = gen_label_rtx (); + emit_jump_insn (gen_arm_cond_branch (label, comparison, cond)); + emit_move_insn (target, mem); + emit_label (label); + + insn_code icode; + + /* We don't support TImode on Arm, but that can't currently be generated + for integral types on this architecture. */ + switch (mode) + { + case E_QImode: icode = CODE_FOR_nospeculateqi; break; + case E_HImode: icode = CODE_FOR_nospeculatehi; break; + case E_SImode: icode = CODE_FOR_nospeculatesi; break; + case E_DImode: icode = CODE_FOR_nospeculatedi; break; + default: + gcc_unreachable (); + } + + emit_insn (GEN_FCN (icode) (tgt2, comparison, cond, target, const0_rtx)); + + if (tgt2 != result) + emit_move_insn (result, tgt2); + + return result; +} + #if CHECKING_P namespace selftest { diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index d60c5af..e700fdf 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -9488,7 +9488,7 @@ (set_attr "type" "multiple")] ) -(define_insn "*cmp_ior" +(define_insn "cmp_ior" [(set (match_operand 6 "dominant_cc_register" "") (compare (ior:SI @@ -12015,6 +12015,44 @@ [(set_attr "length" "4") (set_attr "type" "coproc")]) +(define_insn "nospeculate" + [(set (match_operand:QHSI 0 "s_register_operand" "=l,l,r") + (unspec_volatile:QHSI + [(match_operator 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:QHSI 3 "s_register_operand" "0,0,0") + (match_operand:QHSI 4 "arm_not_operand" "I,K,r")] + VUNSPEC_NOSPECULATE))] + "TARGET_32BIT" + { + if (TARGET_THUMB) + return \"it\\t%d1\;mov%d1\\t%0, %4\;.inst 0xf3af8014\t%@ CSDB\"; + return \"mov%d1\\t%0, %4\;.inst 0xe320f014\t%@ CSDB\"; + } + [(set_attr "type" "mov_imm,mvn_imm,mov_reg") + (set_attr "conds" "use") + (set_attr "length" "8")] +) + +(define_insn "nospeculatedi" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (unspec_volatile:DI + [(match_operator 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:DI 3 "s_register_operand" "0") + (match_operand:DI 4 "arm_rhs_operand" "rI")] + VUNSPEC_NOSPECULATE))] + "TARGET_32BIT" + { + if (TARGET_THUMB) + return \"it\\t%d1\;mov%d1\\t%Q0, %Q4\;it\\t%d1\;mov%d1\\t%R0, %R4\;.inst 0xf3af8014\t%@ CSDB\"; + return \"mov%d1\\t%Q0, %Q4\;mov%d1\\t%R0, %R4\;.inst 0xe320f014\t%@ CSDB\"; + } + [(set_attr "type" "mov_reg") + (set_attr "conds" "use") + (set_attr "length" "12")] +) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index c474f4b..727a5ab 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -168,6 +168,7 @@ VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction. VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction. VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction. + VUNSPEC_NOSPECULATE ; Represent a despeculation sequence. ]) ;; Enumerators for NEON unspecs.