From patchwork Fri Mar 25 09:28:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 787 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:45:47 -0000 Delivered-To: patches@linaro.org Received: by 10.42.161.68 with SMTP id s4cs165084icx; Fri, 25 Mar 2011 02:28:32 -0700 (PDT) Received: by 10.227.1.151 with SMTP id 23mr485169wbf.175.1301045311228; Fri, 25 Mar 2011 02:28:31 -0700 (PDT) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id d17si1231319wbh.28.2011.03.25.02.28.30 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 25 Mar 2011 02:28:31 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of richard.sandiford@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of richard.sandiford@linaro.org) smtp.mail=richard.sandiford@linaro.org Received: by wyb33 with SMTP id 33so382806wyb.37 for ; Fri, 25 Mar 2011 02:28:30 -0700 (PDT) Received: by 10.216.82.14 with SMTP id n14mr485996wee.56.1301045310443; Fri, 25 Mar 2011 02:28:30 -0700 (PDT) Received: from richards-thinkpad (gbibp9ph1--blueice2n1.emea.ibm.com [195.212.29.75]) by mx.google.com with ESMTPS id t72sm265973wei.44.2011.03.25.02.28.28 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 25 Mar 2011 02:28:29 -0700 (PDT) From: Richard Sandiford To: Richard Earnshaw Mail-Followup-To: Richard Earnshaw , gcc-patches@gcc.gnu.org, patches@linaro.org, richard.sandiford@linaro.org Cc: gcc-patches@gcc.gnu.org, patches@linaro.org Subject: Re: Tighten ARM's CANNOT_CHANGE_MODE_CLASS References: <1300985270.12868.95.camel@e102346-lin.cambridge.arm.com> Date: Fri, 25 Mar 2011 09:28:27 +0000 In-Reply-To: <1300985270.12868.95.camel@e102346-lin.cambridge.arm.com> (Richard Earnshaw's message of "Thu, 24 Mar 2011 16:47:50 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1 (gnu/linux) MIME-Version: 1.0 Richard Earnshaw writes: > On Thu, 2011-03-24 at 15:40 +0000, Richard Sandiford wrote: >> gcc/ >> * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS >> case to VFPv1. >> > > GCC doesn't support VFPv1 (see the all_fpus table), and I don't think > many chips based on that ever escaped into the wild world, so I'm not > worried about trying to add that now. > > So it's probably safe to just kill that check for VFP entirely. Even better. :-) How does this look? Tested on arm-linux-gnueabi, no regressions. Richard gcc/ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS case to VFPv1. Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h 2011-03-24 17:21:52.000000000 +0000 +++ gcc/config/arm/arm.h 2011-03-24 18:39:09.000000000 +0000 @@ -1167,12 +1167,10 @@ #define IRA_COVER_CLASSES \ } /* FPA registers can't do subreg as all values are reformatted to internal - precision. VFP registers may only be accessed in the mode they - were set. */ -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ - ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ - || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ + precision. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ : 0) /* The class value for index registers, and the one for base regs. */