From patchwork Sat Feb 22 16:48:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 25136 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f200.google.com (mail-ob0-f200.google.com [209.85.214.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id ADED7203C6 for ; Sat, 22 Feb 2014 16:49:26 +0000 (UTC) Received: by mail-ob0-f200.google.com with SMTP id wp4sf2542892obc.3 for ; Sat, 22 Feb 2014 08:49:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=wLs9NrAuM4UiROshUEiXAQF38oL8NjkStyR+Y7muYUs=; b=ScqaBYtr8FzueqliHZmLq1XejR5wACiVHosCtCp+U6gPMmVuZv4f8eUivvrZONr2Qk 1qNakkNr+lHJ6eDvo5XqYWZ7s4+MYDWNk4KLFtjFMKp1AydGv4V114oR/EGXjfuiBedd hcieL4FVoIPvlzrfn1uFcVrqPkFA+xTy846YKhmWhC8+ekE9ABRjukDp136vlDmxA/ts oOdiCX7wqpj+jNCcQN/wz0xtWmhe+/GJlu1ky/t1iYALGmgOxYxnXR0kv+PX42pl00il AgAVpYBOHJhSW0QasOyiEOWOoRWj0BjSM/POOG5SCQC/dn0S4DqiK+oQpmTgimVFQFDJ JB9g== X-Gm-Message-State: ALoCoQnGzpJnpxkQReKTZlS+N5lrPkmQlLZqs0D1hsbf6rfflTziYVhH+qKJ6gzZL/uwFmeUIVSf X-Received: by 10.182.213.5 with SMTP id no5mr4927592obc.15.1393087766228; Sat, 22 Feb 2014 08:49:26 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.24.226 with SMTP id 89ls249289qgr.14.gmail; Sat, 22 Feb 2014 08:49:26 -0800 (PST) X-Received: by 10.52.107.35 with SMTP id gz3mr6816004vdb.8.1393087766065; Sat, 22 Feb 2014 08:49:26 -0800 (PST) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id e9si4279437vct.34.2014.02.22.08.49.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:26 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id lf12so4430696vcb.17 for ; Sat, 22 Feb 2014 08:49:26 -0800 (PST) X-Received: by 10.221.26.10 with SMTP id rk10mr8274634vcb.0.1393087765977; Sat, 22 Feb 2014 08:49:25 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp114921vcz; Sat, 22 Feb 2014 08:49:25 -0800 (PST) X-Received: by 10.14.94.135 with SMTP id n7mr15348746eef.40.1393087764861; Sat, 22 Feb 2014 08:49:24 -0800 (PST) Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by mx.google.com with ESMTPS id i7si23554289eem.43.2014.02.22.08.49.24 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:24 -0800 (PST) Received-SPF: neutral (google.com: 209.85.215.181 is neither permitted nor denied by best guess record for domain of omair.javaid@linaro.org) client-ip=209.85.215.181; Received: by mail-ea0-f181.google.com with SMTP id k10so2207186eaj.40 for ; Sat, 22 Feb 2014 08:49:24 -0800 (PST) X-Received: by 10.14.203.71 with SMTP id e47mr14836103eeo.99.1393087764426; Sat, 22 Feb 2014 08:49:24 -0800 (PST) Received: from localhost.localdomain ([175.110.189.84]) by mx.google.com with ESMTPSA id a2sm25596112eem.18.2014.02.22.08.49.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:23 -0800 (PST) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org, Omair Javaid Subject: [PATCH 1/5] Support for recording arm/thumb mode coprocessor instructions Date: Sat, 22 Feb 2014 21:48:51 +0500 Message-Id: <1393087735-19261-2-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> References: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2013-02-22 Omair Javaid * arm-tdep.c (arm_record_coproc_data_proc): Updated. (arm_record_asimd_vfp_coproc): New function. (thumb2_record_coproc_insn): New function. (thumb2_record_decode_insn_handler): Updated. (decode_insn): Updated. --- gdb/arm-tdep.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 112 insertions(+), 8 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 12254ec..5eb7b12 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11915,20 +11915,81 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Handling opcode 110 insns. */ + +static int +arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) +{ + uint32_t op, op1, op1_sbit, op1_ebit, coproc; + + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1 = bits (arm_insn_r->arm_insn, 20, 25); + op1_sbit = bit (arm_insn_r->arm_insn, 24); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + op = bit (arm_insn_r->arm_insn, 4); + + if ((coproc & 0x0e) == 0x0a) + { + /* Handle extension register ld/st instructions. */ + if (!(op1 & 0x20)) + return arm_record_unsupported_insn (arm_insn_r); + + /* 64-bit transfers between arm core and extension registers. */ + if ((op1 & 0x3e) == 0x04) + return arm_record_unsupported_insn (arm_insn_r); + } + else + { + /* Handle coprocessor ld/st instructions. */ + if (!(op1 & 0x3a)) + { + /* Store. */ + if (!op1_ebit) + return arm_record_unsupported_insn (arm_insn_r); + else + /* Load. */ + return arm_record_unsupported_insn (arm_insn_r); + } + + /* Move to coprocessor from two arm core registers. */ + if (op1 == 0x4) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to two arm core registers from coprocessor. */ + if (op1 == 0x5) + { + uint32_t reg_t[2]; + + reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); + reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); + return 0; + } + } + return arm_record_unsupported_insn (arm_insn_r); +} + /* Handling opcode 111 insns. */ static int arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { + uint32_t op, op1_sbit, op1_ebit, coproc; struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); struct regcache *reg_cache = arm_insn_r->regcache; uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ ULONGEST u_regval = 0; arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1_sbit = bit (arm_insn_r->arm_insn, 24); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + op = bit (arm_insn_r->arm_insn, 4); /* Handle arm SWI/SVC system call instructions. */ - if (15 == arm_insn_r->opcode) + if (op1_sbit) { if (tdep->arm_syscall_record != NULL) { @@ -11942,20 +12003,52 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) regcache_raw_read_unsigned (reg_cache, 7, &svc_number); ret = tdep->arm_syscall_record (reg_cache, svc_number); + return ret; } else { printf_unfiltered (_("no syscall record support\n")); - ret = -1; + return -1; } } + + if ((coproc & 0x0e) == 0x0a) + { + /* VFP data-processing instructions. */ + if (!op1_sbit && !op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Advanced SIMD, VFP instructions. */ + if (!op1_sbit && op) + return arm_record_unsupported_insn (arm_insn_r); + } else { - arm_record_unsupported_insn (arm_insn_r); - ret = -1; + /* Coprocessor data operations. */ + if (!op1_sbit && !op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to Coprocessor from ARM core register. */ + if (!op1_sbit && !op1_ebit && op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to arm core register from coprocessor. */ + if (!op1_sbit && op1_ebit && op) + { + uint32_t record_buf[1]; + + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + if (record_buf[0] == 15) + record_buf[0] = ARM_PS_REGNUM; + + arm_insn_r->reg_rec_count = 1; + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, + record_buf); + return 0; + } } - return ret; + return arm_record_unsupported_insn (arm_insn_r); } /* Handling opcode 000 insns. */ @@ -12871,6 +12964,17 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) return ARM_RECORD_SUCCESS; } +/* Record handler for thumb32 coprocessor instructions. */ + +static int +thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) +{ + if (bit (thumb2_insn_r->arm_insn, 25)) + return arm_record_coproc_data_proc (thumb2_insn_r); + else + return arm_record_asimd_vfp_coproc (thumb2_insn_r); +} + /* Decodes thumb2 instruction type and invokes its record handler. */ static unsigned int @@ -12902,7 +13006,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } else if (op1 == 0x02) @@ -12968,7 +13072,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } @@ -13012,7 +13116,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, arm_record_ld_st_reg_offset, /* 011. */ arm_record_ld_st_multiple, /* 100. */ arm_record_b_bl, /* 101. */ - arm_record_unsupported_insn, /* 110. */ + arm_record_asimd_vfp_coproc, /* 110. */ arm_record_coproc_data_proc /* 111. */ };