From patchwork Sat Feb 22 16:48:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 25138 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f72.google.com (mail-oa0-f72.google.com [209.85.219.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 276F7203C6 for ; Sat, 22 Feb 2014 16:49:32 +0000 (UTC) Received: by mail-oa0-f72.google.com with SMTP id i4sf21741458oah.3 for ; Sat, 22 Feb 2014 08:49:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=eWPwMq7I1VG+pF38cqmikQm9+83uDa5V8MJIY7J33+I=; b=PGdpVFYvU4mNYyf+a7U5GKvka2kH119aUFIU1F4lz1dyiDua6ySsrtpde+SlHvgMi4 kDPc2b0/Bc4wwZXYIS9K2/wfAeXdc+/fgBvWJpk86A9w4wkq0fglybmWaUM9s6X38SEg 9w2gjJj3d+lcuRPlrD/dIHgDhPcNXzwG9IXvsDMKoMeZhpZYIG4hsa6jGzLR63/Yz6F6 3HkmWXZRZut22F6ScbHHAkb/GQs3LC5Pq2qo+WZL9ZFucvvWJss+KTDA5aL0UpE1TDs0 IACm16IFv7KWA7qPzlqetMiHMAzyBgr/bYp9lpB85dDptBbnwtbtZIodHAZtToLvpp1Y tAHQ== X-Gm-Message-State: ALoCoQmXcHmFZ9CVDKqsNTjpDCtkO3dGeMK9VVi8RB1s+Zr6OZcu4QOsbxYd4r2/QxffJG+oBfjP X-Received: by 10.182.22.133 with SMTP id d5mr5147473obf.27.1393087771668; Sat, 22 Feb 2014 08:49:31 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.86.51 with SMTP id o48ls1412370qgd.83.gmail; Sat, 22 Feb 2014 08:49:31 -0800 (PST) X-Received: by 10.221.29.137 with SMTP id ry9mr8255802vcb.6.1393087771478; Sat, 22 Feb 2014 08:49:31 -0800 (PST) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id uo16si4266555veb.124.2014.02.22.08.49.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:31 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id lg15so766735vcb.26 for ; Sat, 22 Feb 2014 08:49:31 -0800 (PST) X-Received: by 10.52.61.168 with SMTP id q8mr6838873vdr.40.1393087771400; Sat, 22 Feb 2014 08:49:31 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp114926vcz; Sat, 22 Feb 2014 08:49:30 -0800 (PST) X-Received: by 10.14.216.193 with SMTP id g41mr15304516eep.13.1393087770318; Sat, 22 Feb 2014 08:49:30 -0800 (PST) Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by mx.google.com with ESMTPS id x48si23571484eep.3.2014.02.22.08.49.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:30 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.54 is neither permitted nor denied by best guess record for domain of omair.javaid@linaro.org) client-ip=74.125.83.54; Received: by mail-ee0-f54.google.com with SMTP id c41so1340495eek.41 for ; Sat, 22 Feb 2014 08:49:29 -0800 (PST) X-Received: by 10.15.42.136 with SMTP id u8mr15401698eev.52.1393087769713; Sat, 22 Feb 2014 08:49:29 -0800 (PST) Received: from localhost.localdomain ([175.110.189.84]) by mx.google.com with ESMTPSA id a2sm25596112eem.18.2014.02.22.08.49.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:29 -0800 (PST) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org, Omair Javaid Subject: [PATCH 3/5] Support for recording VFP data processing instructions Date: Sat, 22 Feb 2014 21:48:53 +0500 Message-Id: <1393087735-19261-4-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> References: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2013-02-22 Omair Javaid * arm-tdep.c (arm_record_coproc_data_proc): Updated. (arm_record_vfp_data_proc_insn): New function. --- gdb/arm-tdep.c | 221 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 216 insertions(+), 5 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 76466c4..d0d9843 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11915,6 +11915,217 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for arm/thumb mode VFP data processing instructions. */ + +static int +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; + uint32_t record_buf[4]; + uint8_t insn_type = -1; + + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + opc1 = bits (arm_insn_r->arm_insn, 20, 23); + opc2 = bits (arm_insn_r->arm_insn, 16, 19); + opc3 = bits (arm_insn_r->arm_insn, 6, 7); + dp_op_sz = bit (arm_insn_r->arm_insn, 8); + bit_d = bit (arm_insn_r->arm_insn, 22); + opc1 = opc1 & 0x04; + + /* Handle VMLA, VMLS. */ + if (opc1 == 0x00) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VNMLA, VNMLS, VNMUL. */ + else if (opc1 == 0x01) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VMUL. */ + else if (opc1 == 0x02 && !(opc3 & 0x01)) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VADD, VSUB. */ + else if (opc1 == 0x03) + { + if (!bit (arm_insn_r->arm_insn, 9)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VDIV. */ + else if (opc1 == 0x0b) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle all other vfp data processing instructions. */ + else if (opc1 == 0x0b) + { + /* Handle VMOV. */ + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VNEG and VABS. */ + else if ((opc2 == 0x01 && opc3 == 0x01) + || (opc2 == 0x00 && opc3 == 0x03)) + { + if (!bit (arm_insn_r->arm_insn, 11)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VSQRT. */ + else if (opc2 == 0x01 && opc3 == 0x03) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VCVT. */ + else if (opc2 == 0x07 && opc3 == 0x03) + { + if (!dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + else if (opc3 & 0x01) + { + /* Handle VCVT. */ + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) + { + if (!bit (arm_insn_r->arm_insn, 18)) + insn_type = 2; + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VCVT. */ + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VCVTB, VCVTT. */ + else if ((opc2 & 0x0e) == 0x02) + insn_type = 2; + /* Handle VCMP, VCMPE. */ + else if ((opc2 & 0x0e) == 0x04) + insn_type = 3; + } + } + + switch (insn_type) + { + case 0: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + break; + + case 1: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case 2: + reg_vd = (reg_vd << 1) | bit_d; + record_buf[0] = reg_vd + num_regs; + arm_insn_r->reg_rec_count = 1; + break; + + case 3: + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; +} + /* Handling opcode 110 insns. */ static int @@ -12016,21 +12227,21 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { /* VFP data-processing instructions. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vfp_data_proc_insn (arm_insn_r); /* Advanced SIMD, VFP instructions. */ if (!op1_sbit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); } else { /* Coprocessor data operations. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); /* Move to Coprocessor from ARM core register. */ if (!op1_sbit && !op1_ebit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); /* Move to arm core register from coprocessor. */ if (!op1_sbit && op1_ebit && op) @@ -12048,7 +12259,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) } } - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); } /* Handling opcode 000 insns. */