From patchwork Wed Aug 13 13:12:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 35353 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yk0-f198.google.com (mail-yk0-f198.google.com [209.85.160.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4C63A203C5 for ; Wed, 13 Aug 2014 13:13:32 +0000 (UTC) Received: by mail-yk0-f198.google.com with SMTP id q200sf34255210ykb.1 for ; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Wf+PHFNX/a3mWMjnev9np0dRdVkqPoikWoR5TGlEr2M=; b=AfyEtZeFeqOsWISvDo+q/5jhEn7gAWqNIuB3MXIXymG4SN3sMV9ytgV2nijaE9CCYa MAvKWbkev7KjgbIv0F/GwdtO/5xln/sWtD25SU0sFF0EouKY2BLYYrt/ikfy4/QMXYVO poSisYmy+NZvqtl4j6inCaXnzk89FTth5rr91LOS2itao1IZZOvqiSWbICuawNUAAWla p8Czl7nnMWjOw257PcHkySaEK0V7bA9Ai+Uw4oF/4F+G1pzqJ8M4bo6pTeT5qcpFWqj1 P3b2rScRajbrnMogVUm7EVi4iJqLIU/7t03wu82ASLBY29w8GLzYrKq/8gUWIsv3qjcO kkxQ== X-Gm-Message-State: ALoCoQkxVFQL+zJPQ4Ew1mwd/4b6X1PgYrE2Xk8TusmY+2KRgeSQZpkQHKoxaDj0L2obLMxZ/RFp X-Received: by 10.236.118.195 with SMTP id l43mr220126yhh.52.1407935612115; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.81.200 with SMTP id f66ls519483qgd.24.gmail; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) X-Received: by 10.52.87.144 with SMTP id ay16mr1002638vdb.43.1407935611999; Wed, 13 Aug 2014 06:13:31 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id 3si1074966vct.27.2014.08.13.06.13.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:31 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id ik5so15001598vcb.34 for ; Wed, 13 Aug 2014 06:13:31 -0700 (PDT) X-Received: by 10.52.94.108 with SMTP id db12mr2966150vdb.8.1407935611922; Wed, 13 Aug 2014 06:13:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp329761vcb; Wed, 13 Aug 2014 06:13:30 -0700 (PDT) X-Received: by 10.194.119.193 with SMTP id kw1mr4514571wjb.82.1407935610154; Wed, 13 Aug 2014 06:13:30 -0700 (PDT) Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id hj14si2494498wib.78.2014.08.13.06.13.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:30 -0700 (PDT) Received-SPF: pass (google.com: domain of omair.javaid@linaro.org designates 74.125.82.178 as permitted sender) client-ip=74.125.82.178; Received: by mail-we0-f178.google.com with SMTP id w61so11424605wes.37 for ; Wed, 13 Aug 2014 06:13:29 -0700 (PDT) X-Received: by 10.194.237.194 with SMTP id ve2mr4369221wjc.89.1407935609654; Wed, 13 Aug 2014 06:13:29 -0700 (PDT) Received: from localhost.localdomain ([182.185.185.192]) by mx.google.com with ESMTPSA id w14sm50806711wij.2.2014.08.13.06.13.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Aug 2014 06:13:28 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org Subject: [PATCH v3 1/6] Implements support for recording arm/thumb mode coprocessor instructions Date: Wed, 13 Aug 2014 18:12:10 +0500 Message-Id: <1407935535-27978-2-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> References: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2014-08-13 Omair Javaid * arm-tdep.c (arm_record_coproc_data_proc): Updated. (arm_record_asimd_vfp_coproc): Added record handler for asimd, vfp and coprocessor insn. (thumb2_record_coproc_insn): New function. (thumb2_record_decode_insn_handler): Updated. (decode_insn): Updated. --- gdb/arm-tdep.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 112 insertions(+), 10 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index b746eee..607b92e 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11990,20 +11990,80 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Handling opcode 110 insns. */ + +static int +arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) +{ + uint32_t op, op1, op1_sbit, op1_ebit, coproc; + + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1 = bits (arm_insn_r->arm_insn, 20, 25); + op1_sbit = bit (arm_insn_r->arm_insn, 24); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + op = bit (arm_insn_r->arm_insn, 4); + + if ((coproc & 0x0e) == 0x0a) + { + /* Handle extension register ld/st instructions. */ + if (!(op1 & 0x20)) + return arm_record_unsupported_insn (arm_insn_r); + + /* 64-bit transfers between arm core and extension registers. */ + if ((op1 & 0x3e) == 0x04) + return arm_record_unsupported_insn (arm_insn_r); + } + else + { + /* Handle coprocessor ld/st instructions. */ + if (!(op1 & 0x3a)) + { + /* Store. */ + if (!op1_ebit) + return arm_record_unsupported_insn (arm_insn_r); + else + /* Load. */ + return arm_record_unsupported_insn (arm_insn_r); + } + + /* Move to coprocessor from two arm core registers. */ + if (op1 == 0x4) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to two arm core registers from coprocessor. */ + if (op1 == 0x5) + { + uint32_t reg_t[2]; + + reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); + reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); + return 0; + } + } + return arm_record_unsupported_insn (arm_insn_r); +} + /* Handling opcode 111 insns. */ static int arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { + uint32_t op, op1_sbit, op1_ebit, coproc; struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); struct regcache *reg_cache = arm_insn_r->regcache; - uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ ULONGEST u_regval = 0; arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1_sbit = bit (arm_insn_r->arm_insn, 24); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + op = bit (arm_insn_r->arm_insn, 4); /* Handle arm SWI/SVC system call instructions. */ - if (15 == arm_insn_r->opcode) + if (op1_sbit) { if (tdep->arm_syscall_record != NULL) { @@ -12016,21 +12076,52 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) else /* EABI. */ regcache_raw_read_unsigned (reg_cache, 7, &svc_number); - ret = tdep->arm_syscall_record (reg_cache, svc_number); + return tdep->arm_syscall_record (reg_cache, svc_number); } else { printf_unfiltered (_("no syscall record support\n")); - ret = -1; + return -1; } } + + if ((coproc & 0x0e) == 0x0a) + { + /* VFP data-processing instructions. */ + if (!op1_sbit && !op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Advanced SIMD, VFP instructions. */ + if (!op1_sbit && op) + return arm_record_unsupported_insn (arm_insn_r); + } else { - arm_record_unsupported_insn (arm_insn_r); - ret = -1; + /* Coprocessor data operations. */ + if (!op1_sbit && !op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to Coprocessor from ARM core register. */ + if (!op1_sbit && !op1_ebit && op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to arm core register from coprocessor. */ + if (!op1_sbit && op1_ebit && op) + { + uint32_t record_buf[1]; + + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + if (record_buf[0] == 15) + record_buf[0] = ARM_PS_REGNUM; + + arm_insn_r->reg_rec_count = 1; + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, + record_buf); + return 0; + } } - return ret; + return arm_record_unsupported_insn (arm_insn_r); } /* Handling opcode 000 insns. */ @@ -12946,6 +13037,17 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) return ARM_RECORD_SUCCESS; } +/* Record handler for thumb32 coprocessor instructions. */ + +static int +thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) +{ + if (bit (thumb2_insn_r->arm_insn, 25)) + return arm_record_coproc_data_proc (thumb2_insn_r); + else + return arm_record_asimd_vfp_coproc (thumb2_insn_r); +} + /* Decodes thumb2 instruction type and invokes its record handler. */ static unsigned int @@ -12977,7 +13079,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } else if (op1 == 0x02) @@ -13043,7 +13145,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } @@ -13087,7 +13189,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, arm_record_ld_st_reg_offset, /* 011. */ arm_record_ld_st_multiple, /* 100. */ arm_record_b_bl, /* 101. */ - arm_record_unsupported_insn, /* 110. */ + arm_record_asimd_vfp_coproc, /* 110. */ arm_record_coproc_data_proc /* 111. */ };