From patchwork Wed Aug 13 13:12:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 35354 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f200.google.com (mail-pd0-f200.google.com [209.85.192.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 15E57203C5 for ; Wed, 13 Aug 2014 13:13:35 +0000 (UTC) Received: by mail-pd0-f200.google.com with SMTP id w10sf74266533pde.3 for ; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=PaL99OZyyhHW/Q3cEdpslEO/Bg0cASWsxFmq6gqVZzE=; b=RHMlzaqF/CDU36QAateXNMurDVw/CPZF2niDW5TEpNQ7Wj0evTbs4WW4Q866G/twlZ zUrdNqb84vkWdJ/iXHpMbut6uk9j8IPK4k8UuZEWTg99Fejev6nXVgMdHzUkHBchRDcD 1/pELG7Pj4G5mc0C8mPBwB/3SFqSQb58PebmEE06JqcUpiFfpdW9rxAYVK8KrjR0qk2N OGu1Tvwf43oHeXzdWUHuiD2Om8caXsJLEFfe5+OCyRS4/8Pze/Tls87F4o12HrC1+TzW pZop6B1yfPP1z/CqBitXY9bEWyS9EHKjzg1fJ1/FnfonAQq0vR0e/QNab7Jke5vkjmGw AiEw== X-Gm-Message-State: ALoCoQlCso2Y9PAg9JxR+P5Bp56NRxSFikOTorbH0weeSw9GTIsXKAV0U0KrMFb9yKdpRmg9mIRk X-Received: by 10.66.168.197 with SMTP id zy5mr2351962pab.7.1407935614363; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.92.228 with SMTP id b91ls511216qge.88.gmail; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) X-Received: by 10.52.127.5 with SMTP id nc5mr508050vdb.59.1407935614012; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id va7si1075321vcb.25.2014.08.13.06.13.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:34 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id lf12so15015961vcb.12 for ; Wed, 13 Aug 2014 06:13:33 -0700 (PDT) X-Received: by 10.52.129.200 with SMTP id ny8mr2894598vdb.27.1407935613935; Wed, 13 Aug 2014 06:13:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp329762vcb; Wed, 13 Aug 2014 06:13:33 -0700 (PDT) X-Received: by 10.194.184.101 with SMTP id et5mr4618741wjc.14.1407935612664; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) Received: from mail-wg0-f45.google.com (mail-wg0-f45.google.com [74.125.82.45]) by mx.google.com with ESMTPS id lv10si2148376wjb.90.2014.08.13.06.13.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:32 -0700 (PDT) Received-SPF: pass (google.com: domain of omair.javaid@linaro.org designates 74.125.82.45 as permitted sender) client-ip=74.125.82.45; Received: by mail-wg0-f45.google.com with SMTP id x12so11119969wgg.28 for ; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) X-Received: by 10.180.80.133 with SMTP id r5mr38311286wix.62.1407935612166; Wed, 13 Aug 2014 06:13:32 -0700 (PDT) Received: from localhost.localdomain ([182.185.185.192]) by mx.google.com with ESMTPSA id w14sm50806711wij.2.2014.08.13.06.13.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Aug 2014 06:13:31 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org Subject: [PATCH v3 2/6] Implements support for recording thumb2 ASIMD struct ld/st insn Date: Wed, 13 Aug 2014 18:12:11 +0500 Message-Id: <1407935535-27978-3-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> References: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2014-08-13 Omair Javaid * arm-tdep.c (thumb2_record_asimd_struct_ld_st): Added record handler for advance SIMD struct ld/st insn. (thumb2_record_decode_insn_handler): Updated. --- gdb/arm-tdep.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 191 insertions(+), 1 deletion(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 607b92e..adee197 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -13048,6 +13048,196 @@ thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) return arm_record_asimd_vfp_coproc (thumb2_insn_r); } +/* Record handler for advance SIMD structure load/store instructions. */ + +static int +thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) +{ + struct regcache *reg_cache = thumb2_insn_r->regcache; + uint32_t l_bit, a_bit, b_bits; + uint32_t record_buf[128], record_buf_mem[128]; + uint32_t reg_rn, reg_vd, address, f_esize, f_elem; + uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; + uint8_t bf_align, f_ebytes; + + l_bit = bit (thumb2_insn_r->arm_insn, 21); + a_bit = bit (thumb2_insn_r->arm_insn, 23); + b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); + bf_align = bits (thumb2_insn_r->arm_insn, 4, 5); + reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); + reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); + reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; + f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); + f_esize = 8 * f_ebytes; + f_elem = 8 / f_ebytes; + + if (!l_bit) + { + ULONGEST u_regval = 0; + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + address = u_regval; + + if (!a_bit) + { + /* Handle VST1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + { + if (b_bits == 0x07) + bf_regs = 1; + else if (b_bits == 0x0a) + bf_regs = 2; + else if (b_bits == 0x06) + bf_regs = 3; + else if (b_bits == 0x02) + bf_regs = 4; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address; + address = address + f_ebytes; + thumb2_insn_r->mem_rec_count += 1; + } + } + } + /* Handle VST2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + { + if (b_bits == 0x09 || b_bits == 0x08) + bf_regs = 1; + else if (b_bits == 0x03) + bf_regs = 2; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 2; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (2 * f_ebytes); + } + } + /* Handle VST3. */ + else if ((b_bits & 0x0e) == 0x04) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 3; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (3 * f_ebytes); + } + } + /* Handle VST4. */ + else if (!(b_bits & 0x0e)) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 4; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (4 * f_ebytes); + } + } + } + else + { + uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); + + if (bft_size == 0x00) + f_ebytes = 1; + else if (bft_size == 0x01) + f_ebytes = 2; + else if (bft_size == 0x02) + f_ebytes = 4; + else + f_ebytes = 0; + + /* Handle VST1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08) + thumb2_insn_r->mem_rec_count = 1; + /* Handle VST2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) + thumb2_insn_r->mem_rec_count = 2; + /* Handle VST3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) + thumb2_insn_r->mem_rec_count = 3; + /* Handle VST4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) + thumb2_insn_r->mem_rec_count = 4; + + for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) + { + record_buf_mem[index_m] = f_ebytes; + record_buf_mem[index_m] = address + (index_m * f_ebytes); + } + } + } + else + { + if (!a_bit) + { + /* Handle VLD1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0e) == 0x04) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if (!(b_bits & 0x0e)) + thumb2_insn_r->reg_rec_count = 4; + } + else + { + /* Handle VLD1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) + thumb2_insn_r->reg_rec_count = 4; + + for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) + record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; + } + } + + if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) + { + record_buf[index_r] = reg_rn; + thumb2_insn_r->reg_rec_count += 1; + } + + REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, + record_buf); + MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, + record_buf_mem); + return 0; +} + /* Decodes thumb2 instruction type and invokes its record handler. */ static unsigned int @@ -13110,7 +13300,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (!((op2 & 0x71) ^ 0x10)) { /* Advanced SIMD or structure load/store instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); } else if (!((op2 & 0x67) ^ 0x01)) {