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[209.132.180.131]) by mx.google.com with ESMTPS id j23-v6si21833303pgn.139.2018.09.04.13.46.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Sep 2018 13:46:52 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-95671-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BuCzRW5c; dkim=pass header.i=@linaro.org header.s=google header.b=LSsIFyzO; spf=pass (google.com: domain of libc-alpha-return-95671-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-95671-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=XqwLxg1P1ambzOAXSgD1T34KxFPm1Zk 4CWvQ4wocuBjHSf0jeVmf/ExB1SDKK5160liTyswoH6GokzCCsKJoOz0DEAX600i AZz6a3bBC38zEt23te/fpu3GHXB5hutU9nyrxK9zpRHsh/BhL0wGIofoj0QuxSlv OFTe8EcGe2+Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=J3wIIrY3fxfSAaeR/zeqglPu78M=; b=BuCzR W5cQWWlHWwsok4mZosN1Kgb3z8pl1DZxkTh1NCIkxG2FOE5ldtkVKd7k/QUYOnd1 4zaYi3hfmsWACIlc4a2r30xSnaaCDtu/cGZqb5kMsDOQUGuWdSc+Gb1KhEGG5YDB mWMbk8iAojo0Dlr1VsiX5PjixDbzsah7z73p9Q= Received: (qmail 34345 invoked by alias); 4 Sep 2018 20:46:10 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 34146 invoked by uid 89); 4 Sep 2018 20:46:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SEM_URI, SEM_URIRED, SPF_PASS autolearn=ham version=3.3.2 spammy=proves, expects X-HELO: mail-qk1-f195.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=gzhUnGrl2CIILyE/qLsnzPtwIrjHGrO0EU8entvzrpg=; b=LSsIFyzOtsD/rDSOKKw/n2Tv6wUkfXtOIaN68E4TgnhCgiX7JWecNNo2wi/IHj/sma N5xoI/IHmRAeyJmGSX/f1BEfT9+WXVtsbSMUI0Dn8Y095NJJqHEuiTURQdWeLrpvpZfS vql2A65P0zvHXLJVj/dubNyXE/WHoIemtx5uk= Return-Path: From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 4/7] x86: Remove wrong THREAD_ATOMIC_* macros Date: Tue, 4 Sep 2018 17:45:50 -0300 Message-Id: <20180904204553.6971-5-adhemerval.zanella@linaro.org> In-Reply-To: <20180904204553.6971-1-adhemerval.zanella@linaro.org> References: <20180904204553.6971-1-adhemerval.zanella@linaro.org> The x86 defines optimized THREAD_ATOMIC_* macros where reference always the current thread instead of the one indicated by input 'descr' argument. It work as long the input is the self thread pointer, however it generates wrong code is the semantic is to set a bit atomicialy from another thread. This is not an issue for current GLIBC usage, however the new cancellation code expects that some synchronization code to atomically set bits from different threads. The generic code generates an additional load to reference to TLS segment, for instance the code: THREAD_ATOMIC_BIT_SET (THREAD_SELF, cancelhandling, CANCELED_BIT); Compiles to: lock;orl $4, %fs:776 Where with patch changes it now compiles to: mov %fs:16,%rax lock;orl $4, 776(%rax) If some usage indeed proves to be a hotspot we can add an extra macro with a more descriptive name (THREAD_ATOMIC_BIT_SET_SELF for instance) where x86_64 might optimize it. Checked on x86_64-linux-gnu. * sysdeps/x86_64/nptl/tls.h (THREAD_ATOMIC_CMPXCHG_VAL, THREAD_ATOMIC_AND, THREAD_ATOMIC_BIT_SET): Remove macros. --- ChangeLog | 3 +++ sysdeps/x86_64/nptl/tls.h | 37 ------------------------------------- 2 files changed, 3 insertions(+), 37 deletions(-) -- 2.17.1 diff --git a/sysdeps/x86_64/nptl/tls.h b/sysdeps/x86_64/nptl/tls.h index e88561c934..835a0d3deb 100644 --- a/sysdeps/x86_64/nptl/tls.h +++ b/sysdeps/x86_64/nptl/tls.h @@ -306,43 +306,6 @@ _Static_assert (offsetof (tcbhead_t, __glibc_unused2) == 0x80, }}) -/* Atomic compare and exchange on TLS, returning old value. */ -# define THREAD_ATOMIC_CMPXCHG_VAL(descr, member, newval, oldval) \ - ({ __typeof (descr->member) __ret; \ - __typeof (oldval) __old = (oldval); \ - if (sizeof (descr->member) == 4) \ - asm volatile (LOCK_PREFIX "cmpxchgl %2, %%fs:%P3" \ - : "=a" (__ret) \ - : "0" (__old), "r" (newval), \ - "i" (offsetof (struct pthread, member))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); \ - __ret; }) - - -/* Atomic logical and. */ -# define THREAD_ATOMIC_AND(descr, member, val) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "andl %1, %%fs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (val)); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - -/* Atomic set bit. */ -# define THREAD_ATOMIC_BIT_SET(descr, member, bit) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "orl %1, %%fs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (1 << (bit))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - /* Set the stack guard field in TCB head. */ # define THREAD_SET_STACK_GUARD(value) \ THREAD_SETMEM (THREAD_SELF, header.stack_guard, value)