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[209.132.180.131]) by mx.google.com with ESMTPS id e68-v6si22069700plb.38.2018.09.04.13.47.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Sep 2018 13:47:02 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-95672-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=pwHpJ4lS; dkim=pass header.i=@linaro.org header.s=google header.b=iAfrz1HE; spf=pass (google.com: domain of libc-alpha-return-95672-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-95672-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=yiVwDm6Xg71xW6N4tyZJznBCNHc9NSj DtId/sQqSgxwe+yJs298usZ0qh5gCDLs5pI85ROtlwVHsrJ2ZmmeOOwYx3PxXaCc yfM0kL/q37ZHZr7Ah1z9iA1rXbMAb8l6mQ18mG5vpPSiKxWOYHmZtjctX35nEk9j 6AnZ3Z37FJhY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=c2X9oJGmZoB1k+zVLGIoO+KMXpY=; b=pwHpJ 4lSnfA0rxF35Ez4tbdHV8J4JEAK4ZonW00nKpHyisNsroIZmvLQNyh4dBe1Jk5iR bK1Ylvn/9VZeKDZhQqESsYCrs3AXls1UEwOf9vvxJhaUwVvVxUkHfHZjC/9XmHNq 9eeV3CqO00HyfAQ4amRXgY5OolFNkVhNLdXGMc= Received: (qmail 34534 invoked by alias); 4 Sep 2018 20:46:11 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 34394 invoked by uid 89); 4 Sep 2018 20:46:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SEM_URI, SEM_URIRED, SPF_PASS autolearn=ham version=3.3.2 spammy=proves, Hx-languages-length:2502, expects X-HELO: mail-qk1-f170.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=qhYe6UrU7SVOJ3qWYli9JzPtOcdsQDWefh1Yi6BmuIA=; b=iAfrz1HEVERF7vPHpHHjmjxkRDj1ixMw5jE/kOV+WFKzB1KwbmFusaJ/zOcbOPLNvq 01GDBflMvN/erCs1sIG+zTl3Q9GF0yfxo/KwPzNt65zFh7Kgbo7Dwr4UqplSLAAKhkb4 E1v0YC/soL9L2KN5ZOuNH5GNN9e2zZPG/3BTg= Return-Path: From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 5/7] i386: Remove bogus THREAD_ATOMIC_* macros Date: Tue, 4 Sep 2018 17:45:51 -0300 Message-Id: <20180904204553.6971-6-adhemerval.zanella@linaro.org> In-Reply-To: <20180904204553.6971-1-adhemerval.zanella@linaro.org> References: <20180904204553.6971-1-adhemerval.zanella@linaro.org> The x86 defines optimized THREAD_ATOMIC_* macros where reference always the current thread instead of the one indicated by input 'descr' argument. It work as long the input is the self thread pointer, however it generates wrong code is the semantic is to set a bit atomicialy from another thread. This is not an issue for current GLIBC usage, however the new cancellation code expects that some synchronization code to atomically set bits from different threads. If some usage indeed proves to be a hotspot we can add an extra macro with a more descriptive name (THREAD_ATOMIC_BIT_SET_SELF for instance) where i386 might optimize it. Checked on i686-linux-gnu. * sysdeps/i686/nptl/tls.h (THREAD_ATOMIC_CMPXCHG_VAL, THREAD_ATOMIC_AND, THREAD_ATOMIC_BIT_SET): Remove macros. --- ChangeLog | 3 +++ sysdeps/i386/nptl/tls.h | 37 ------------------------------------- 2 files changed, 3 insertions(+), 37 deletions(-) -- 2.17.1 diff --git a/sysdeps/i386/nptl/tls.h b/sysdeps/i386/nptl/tls.h index 12285d3217..22ebf3d741 100644 --- a/sysdeps/i386/nptl/tls.h +++ b/sysdeps/i386/nptl/tls.h @@ -362,43 +362,6 @@ tls_fill_user_desc (union user_desc_init *desc, }}) -/* Atomic compare and exchange on TLS, returning old value. */ -#define THREAD_ATOMIC_CMPXCHG_VAL(descr, member, newval, oldval) \ - ({ __typeof (descr->member) __ret; \ - __typeof (oldval) __old = (oldval); \ - if (sizeof (descr->member) == 4) \ - asm volatile (LOCK_PREFIX "cmpxchgl %2, %%gs:%P3" \ - : "=a" (__ret) \ - : "0" (__old), "r" (newval), \ - "i" (offsetof (struct pthread, member))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); \ - __ret; }) - - -/* Atomic logical and. */ -#define THREAD_ATOMIC_AND(descr, member, val) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "andl %1, %%gs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (val)); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - -/* Atomic set bit. */ -#define THREAD_ATOMIC_BIT_SET(descr, member, bit) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "orl %1, %%gs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (1 << (bit))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - /* Set the stack guard field in TCB head. */ #define THREAD_SET_STACK_GUARD(value) \ THREAD_SETMEM (THREAD_SELF, header.stack_guard, value)