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([2804:1b3:a7c0:3d3c:883c:5760:462b:b60b]) by smtp.gmail.com with ESMTPSA id x11-20020a817c0b000000b005a0f9718a5fsm178739ywc.78.2023.10.30.14.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 14:32:57 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Joseph Myers Subject: [PATCH 5/6] linux: Sync Linux 6.6 elf.h Date: Mon, 30 Oct 2023 18:32:44 -0300 Message-Id: <20231030213245.2626895-6-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030213245.2626895-1-adhemerval.zanella@linaro.org> References: <20231030213245.2626895-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org It adds NT_X86_SHST (2fab02b25ae7cf5), NT_RISCV_CSR/NT_RISCV_VECTOR (9300f00439743c4), and NT_LOONGARCH_HW_BREAK/NT_LOONGARCH_HW_WATCH (1a69f7a161a78ae). --- elf/elf.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/elf/elf.h b/elf/elf.h index 73a64baa79..50b73fa329 100644 --- a/elf/elf.h +++ b/elf/elf.h @@ -796,6 +796,8 @@ typedef struct #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ #define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ #define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ +/* Old binutils treats 0x203 as a CET state */ +#define NT_X86_SHST 0x204 /* x86 SHSTK state */ #define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */ #define NT_S390_TIMER 0x301 /* s390 timer register */ #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */ @@ -834,6 +836,8 @@ typedef struct #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers. */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode. */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers. */ +#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ +#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers. */ @@ -843,6 +847,8 @@ typedef struct SIMD Extension registers. */ #define NT_LOONGARCH_LBT 0xa04 /* LoongArch Loongson Binary Translation registers. */ +#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint registers */ +#define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint registers */ /* Legal values for the note segment descriptor types for object files. */