From patchwork Mon Jan 13 15:04:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 23174 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f199.google.com (mail-ob0-f199.google.com [209.85.214.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DE919202DA for ; Mon, 13 Jan 2014 15:04:16 +0000 (UTC) Received: by mail-ob0-f199.google.com with SMTP id gq1sf28083826obb.6 for ; Mon, 13 Jan 2014 07:04:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=/AOw17KEZIVuUx+D1hLxEFW5rU1DO/TOop4ebvGCqg4=; b=UFYrTG2NbTJQd4OYUBRbk3iXA0H89GpdLAgBpnigewHoc3UnNPbacbHvrTja5tBsuI xIRSbqO1UHI7+W/nOfIVV9sXMKTwIgPm3qzZTm2dVPbXTp86c83Dljy8KM08eJFxf/Ss uSsnEbsoOOYyPkzYY9iymRhyX8faW4zMLfzx+5J7wPQFenntr/MX7444Pn3xh6Ryb79+ 8fC4kM489fWTkPtEAr5yrxhWEcswzBnQ0JNHk/8XxHitJEbZxajU6l5mda59/OnU5kdr NAyMPJqQoKtDgIpH8AxB1WMANk5PrJzcA1oXmAt2IulJkBRi7+9YMjRS2BD2WTbNbVno 1DVA== X-Gm-Message-State: ALoCoQkLMZgunQ6PycbRZPmlwdqlOmF9B0N8AEf/CrHzYyUN47693hEcXXlE/pLMpYQK+72Bl6uP X-Received: by 10.42.84.136 with SMTP id m8mr8813589icl.9.1389625455998; Mon, 13 Jan 2014 07:04:15 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.38.135 with SMTP id g7ls244225qek.62.gmail; Mon, 13 Jan 2014 07:04:15 -0800 (PST) X-Received: by 10.58.255.233 with SMTP id at9mr18278449ved.20.1389625455760; Mon, 13 Jan 2014 07:04:15 -0800 (PST) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by mx.google.com with ESMTPS id ry8si581072vcb.121.2014.01.13.07.04.15 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 13 Jan 2014 07:04:15 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.180; Received: by mail-ve0-f180.google.com with SMTP id jz11so5201262veb.25 for ; Mon, 13 Jan 2014 07:04:15 -0800 (PST) X-Received: by 10.52.236.132 with SMTP id uu4mr1662721vdc.47.1389625455658; Mon, 13 Jan 2014 07:04:15 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.59.13.131 with SMTP id ey3csp134475ved; Mon, 13 Jan 2014 07:04:15 -0800 (PST) X-Received: by 10.15.109.196 with SMTP id cf44mr3419602eeb.12.1389625454669; Mon, 13 Jan 2014 07:04:14 -0800 (PST) Received: from mail-ee0-f51.google.com (mail-ee0-f51.google.com [74.125.83.51]) by mx.google.com with ESMTPS id n47si12141695eey.245.2014.01.13.07.04.13 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 13 Jan 2014 07:04:13 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.51 is neither permitted nor denied by best guess record for domain of taras.kondratiuk@linaro.org) client-ip=74.125.83.51; Received: by mail-ee0-f51.google.com with SMTP id b15so3236079eek.24 for ; Mon, 13 Jan 2014 07:04:13 -0800 (PST) X-Received: by 10.14.212.69 with SMTP id x45mr28603058eeo.69.1389625452735; Mon, 13 Jan 2014 07:04:12 -0800 (PST) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id o13sm40509532eex.19.2014.01.13.07.04.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 13 Jan 2014 07:04:12 -0800 (PST) From: Taras Kondratiuk To: Tero Kristo Cc: patches@linaro.org, linaro-networking@linaro.org, linaro-kernel@lists.linaro.org, Victor Kamensky , Taras Kondratiuk , Tony Lindgren , Russell King , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE Date: Mon, 13 Jan 2014 17:04:06 +0200 Message-Id: <1389625447-24132-1-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: taras.kondratiuk@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Victor Kamensky If kernel operates in BE mode on device that has LE bootloader/ROM code, we need to switch CPU to operate in BE mode before it will start to access BE data. Generic secondary_startup function that is called from OMAP specific secondary startup code will do the switch, but we need to do it earlier because OMAP's secondary_startup code works with BE data. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- This is a part of RFC series [1]. Based on v3.13-rc8. [1] http://www.spinics.net/lists/linux-omap/msg99927.html arch/arm/mach-omap2/omap-headsmp.S | 13 +++++++++++++ arch/arm/mach-omap2/sleep44xx.S | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 75e9295..75c98d4 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -17,6 +17,7 @@ #include #include +#include #include "omap44xx.h" @@ -58,6 +59,12 @@ hold: ldr r12,=0x103 bne hold /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + + /* * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ @@ -75,6 +82,12 @@ hold_2: ldr r12,=0x103 bne hold_2 /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + + /* * GIC distributor control register has changed between * CortexA9 r1pX and r2pX. The Control Register secure * banked version is now composed of 2 bits: diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 9086ce0..e556c8b 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -249,6 +249,12 @@ ENDPROC(omap4_finish_suspend) */ ENTRY(omap4_cpu_resume) /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + + /* * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA * init and for CPU1, a secure PPA API provided. CPU0 must be ON