From patchwork Fri Aug 16 02:25:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 19188 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f72.google.com (mail-yh0-f72.google.com [209.85.213.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 3A6B42486D for ; Fri, 16 Aug 2013 02:27:44 +0000 (UTC) Received: by mail-yh0-f72.google.com with SMTP id z20sf233405yhz.3 for ; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:in-reply-to:references :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=SyVbjnLgxDQaP/OVNrYpMdVMtjDD/tmlskErGAFAew4=; b=JHBwyb38Umce/CyOm3UjXd9LJ+lIRO5TjWYxjTW6Rjg5YmAqSIKSCcuQX5LfAwqTxL ZrmbzW6OiIvVZnfRzuu8WDgjvFtQuZ2/VVW/vr4fsO0TDSWJlaDi5TQdZlICjB988838 kNHdaUZxn0bDaP+2flnaFn6r17MeIyZsXPgNgSUeZlIRzvCrNJzyLWQdMrYR32eJsGcR 2tYjbaZpVtoSHOWVkI71MoSczkguMxHzBCFGwNODWx2rc3/K9knuVxRROpozJsE9PpLG qHm7iYTasj/IYMgz3O5PRfKVlRA8c5ONjdBeX25Zj/Jhql0ttVZ6V9DNb4k8CBNdtWTv Z/iA== X-Received: by 10.236.54.68 with SMTP id h44mr350134yhc.21.1376620063779; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.14.106 with SMTP id o10ls594641qec.36.gmail; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) X-Received: by 10.220.43.19 with SMTP id u19mr17215056vce.3.1376620063660; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) Received: from mail-vb0-f47.google.com (mail-vb0-f47.google.com [209.85.212.47]) by mx.google.com with ESMTPS id ur15si764968veb.32.2013.08.15.19.27.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 15 Aug 2013 19:27:43 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.47; Received: by mail-vb0-f47.google.com with SMTP id h10so1211311vbh.20 for ; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) X-Gm-Message-State: ALoCoQkvfoRkKpsC77VnYabPeUKhbzbYupl/geFcSpiSstzQNCYOxFubaibpEhnpufRwkO6Y5HK6 X-Received: by 10.58.217.167 with SMTP id oz7mr17225637vec.15.1376620063548; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp45197vcz; Thu, 15 Aug 2013 19:27:43 -0700 (PDT) X-Received: by 10.69.0.9 with SMTP id au9mr18932620pbd.62.1376620062611; Thu, 15 Aug 2013 19:27:42 -0700 (PDT) Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by mx.google.com with ESMTPS id y8si51410pax.151.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 15 Aug 2013 19:27:42 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.174 is neither permitted nor denied by best guess record for domain of viresh.kumar@linaro.org) client-ip=209.85.192.174; Received: by mail-pd0-f174.google.com with SMTP id y13so1598629pdi.33 for ; Thu, 15 Aug 2013 19:27:42 -0700 (PDT) X-Received: by 10.66.146.42 with SMTP id sz10mr625523pab.78.1376620062222; Thu, 15 Aug 2013 19:27:42 -0700 (PDT) Received: from localhost ([122.172.193.46]) by mx.google.com with ESMTPSA id sz3sm3109458pbc.5.2013.08.15.19.27.38 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 15 Aug 2013 19:27:41 -0700 (PDT) From: Viresh Kumar To: rjw@sisk.pl Cc: linaro-kernel@lists.linaro.org, patches@linaro.org, cpufreq@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Viresh Kumar , Shawn Guo Subject: [PATCH 15/34] cpufreq: imx6q: remove calls to cpufreq_notify_transition() Date: Fri, 16 Aug 2013 07:55:12 +0530 Message-Id: <91e60ba4e81b89fbdbf2ff495ccfbf8dc7cb6a04.1376619363.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 1.7.12.rc2.18.g61b472e In-Reply-To: References: In-Reply-To: References: X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: viresh.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Most of the drivers do following in their ->target_index() routines: struct cpufreq_freqs freqs; freqs.old = old freq... freqs.new = new freq... cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); /* Change rate here */ cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); This is replicated over all cpufreq drivers today and there doesn't exists a good enough reason why this shouldn't be moved to cpufreq core instead. Earlier patches have added support in cpufreq core to do cpufreq notification on frequency change, this one removes it from this driver. Some related minor cleanups are also done along with it. Cc: Shawn Guo Signed-off-by: Viresh Kumar --- drivers/cpufreq/imx6q-cpufreq.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 04a32fb..f35c674 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -41,14 +41,14 @@ static unsigned int imx6q_get_speed(unsigned int cpu) static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { - struct cpufreq_freqs freqs; struct opp *opp; unsigned long freq_hz, volt, volt_old; + unsigned int old_freq, new_freq; int ret; - freqs.new = freq_table[index].frequency; - freq_hz = freqs.new * 1000; - freqs.old = clk_get_rate(arm_clk) / 1000; + new_freq = freq_table[index].frequency; + freq_hz = new_freq * 1000; + old_freq = clk_get_rate(arm_clk) / 1000; rcu_read_lock(); opp = opp_find_freq_ceil(cpu_dev, &freq_hz); @@ -63,26 +63,23 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) volt_old = regulator_get_voltage(arm_reg); dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", - freqs.old / 1000, volt_old / 1000, - freqs.new / 1000, volt / 1000); - - cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); + old_freq / 1000, volt_old / 1000, + new_freq / 1000, volt / 1000); /* scaling up? scale voltage before frequency */ - if (freqs.new > freqs.old) { + if (new_freq > old_freq) { ret = regulator_set_voltage_tol(arm_reg, volt, 0); if (ret) { dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); - freqs.new = freqs.old; - goto post_notify; + return ret; } /* * Need to increase vddpu and vddsoc for safety * if we are about to run at 1.2 GHz. */ - if (freqs.new == FREQ_1P2_GHZ / 1000) { + if (new_freq == FREQ_1P2_GHZ / 1000) { regulator_set_voltage_tol(pu_reg, PU_SOC_VOLTAGE_HIGH, 0); regulator_set_voltage_tol(soc_reg, @@ -103,13 +100,13 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { - clk_set_rate(pll1_sys_clk, freqs.new * 1000); + clk_set_rate(pll1_sys_clk, new_freq * 1000); /* * If we are leaving 396 MHz set-point, we need to enable * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep * their use count correct. */ - if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) { + if (old_freq * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) { clk_prepare_enable(pll1_sys_clk); clk_disable_unprepare(pll2_pfd2_396m_clk); } @@ -124,16 +121,15 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) } /* Ensure the arm clock divider is what we expect */ - ret = clk_set_rate(arm_clk, freqs.new * 1000); + ret = clk_set_rate(arm_clk, new_freq * 1000); if (ret) { dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); regulator_set_voltage_tol(arm_reg, volt_old, 0); - freqs.new = freqs.old; - goto post_notify; + return ret; } /* scaling down? scale voltage after frequency */ - if (freqs.new < freqs.old) { + if (new_freq < old_freq) { ret = regulator_set_voltage_tol(arm_reg, volt, 0); if (ret) { dev_warn(cpu_dev, @@ -141,7 +137,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) ret = 0; } - if (freqs.old == FREQ_1P2_GHZ / 1000) { + if (old_freq == FREQ_1P2_GHZ / 1000) { regulator_set_voltage_tol(pu_reg, PU_SOC_VOLTAGE_NORMAL, 0); regulator_set_voltage_tol(soc_reg, @@ -149,10 +145,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) } } -post_notify: - cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); - - return ret; + return 0; } static int imx6q_cpufreq_init(struct cpufreq_policy *policy)