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[2001:1868:205::9]) by mx.google.com with ESMTPS id o10si5148740qag.14.2014.06.18.22.45.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jun 2014 22:45:53 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxV8T-0000cw-ER; Thu, 19 Jun 2014 05:43:45 +0000 Received: from mail-qa0-f48.google.com ([209.85.216.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxV8Q-0000b2-Im for linux-arm-kernel@lists.infradead.org; Thu, 19 Jun 2014 05:43:43 +0000 Received: by mail-qa0-f48.google.com with SMTP id x12so1557284qac.21 for ; Wed, 18 Jun 2014 22:43:19 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.140.48.161 with SMTP id o30mr3577859qga.68.1403156599641; Wed, 18 Jun 2014 22:43:19 -0700 (PDT) Received: by 10.229.234.200 with HTTP; Wed, 18 Jun 2014 22:43:19 -0700 (PDT) In-Reply-To: <20140614150507.GI14023@lvm> References: <1402590613-3341-1-git-send-email-victor.kamensky@linaro.org> <1402590613-3341-15-git-send-email-victor.kamensky@linaro.org> <20140614150507.GI14023@lvm> Date: Wed, 18 Jun 2014 22:43:19 -0700 Message-ID: Subject: Re: [PATCH v4 14/14] ARM64: KVM: fix big endian issue in access_vm_reg for 32bit guest From: Victor Kamensky To: Christoffer Dall X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140618_224342_719988_51D76999 X-CRM114-Status: GOOD ( 18.05 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.48 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.216.48 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: "linaro-kernel@lists.linaro.org" , Marc Zyngier , Taras Kondratiuk , Alexander Graf , "kvmarm@lists.cs.columbia.edu" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Hi Christoffer, Please see inline. On 14 June 2014 08:05, Christoffer Dall wrote: > On Thu, Jun 12, 2014 at 09:30:13AM -0700, Victor Kamensky wrote: >> Fix issue with 32bit guests running on top of BE KVM host. >> Indexes of high and low words of 64bit cp15 register are >> swapped in case of big endian code, since 64bit cp15 state is >> restored or saved with double word write or read instruction. >> >> Define helper macros to access high low words of 64bit cp15 >> register. >> >> Signed-off-by: Victor Kamensky >> --- >> arch/arm64/include/asm/kvm_host.h | 8 ++++++++ >> arch/arm64/kvm/sys_regs.c | 4 ++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h >> index 0a1d697..e9d2e11 100644 >> --- a/arch/arm64/include/asm/kvm_host.h >> +++ b/arch/arm64/include/asm/kvm_host.h >> @@ -140,6 +140,14 @@ struct kvm_vcpu_arch { >> #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) >> #define vcpu_cp15(v,r) ((v)->arch.ctxt.cp15[(r)]) >> >> +#ifdef CONFIG_CPU_BIG_ENDIAN >> +#define vcpu_cp15_64_high(v,r) ((v)->arch.ctxt.cp15[((r) + 0)]) >> +#define vcpu_cp15_64_low(v,r) ((v)->arch.ctxt.cp15[((r) + 1)]) >> +#else >> +#define vcpu_cp15_64_high(v,r) ((v)->arch.ctxt.cp15[((r) + 1)]) >> +#define vcpu_cp15_64_low(v,r) ((v)->arch.ctxt.cp15[((r) + 0)]) >> +#endif >> + >> struct kvm_vm_stat { >> u32 remote_tlb_flush; >> }; >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 8e65e31..71aa9b0 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -137,9 +137,9 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, >> if (!p->is_aarch32) { >> vcpu_sys_reg(vcpu, r->reg) = val; >> } else { >> - vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL; >> + vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL; >> if (!p->is_32bit) >> - vcpu_cp15(vcpu, r->reg + 1) = val >> 32; >> + vcpu_cp15_64_high(vcpu, r->reg) = val >> 32; >> } >> return true; >> } >> -- >> 1.8.1.4 >> > > I thought there was a consensus here about handling 64-bit accesses > through the 64-bit values with the vcpu_sys_reg() interface? Did you > give up on this for a particular reason? I think I missed that. Do you want this patch to look like below? Personally, I find it a little bit less clear, but I am fine with it if you like it more. Or you meant something different? commit 2de73290a809ef8dbaed087ef2f86d662a006e36 Author: Victor Kamensky Date: Mon May 12 13:57:21 2014 -0700 ARM64: KVM: fix big endian issue in access_vm_reg for 32bit guest Fix issue with 32bit guests running on top of BE KVM host. Indexes of high and low words of 64bit cp15 register are swapped in case of big endian code, since 64bit cp15 state is restored or saved with double word write or read instruction. Define helper macro to access low words of 64bit cp15 register. Signed-off-by: Victor Kamensky Thanks, Victor > -Christoffer diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a10803c..fce74ce 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -140,6 +140,12 @@ struct kvm_vcpu_arch { #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) #define vcpu_cp15(v,r) ((v)->arch.ctxt.cp15[(r)]) +#ifdef CONFIG_CPU_BIG_ENDIAN +#define vcpu_cp15_64_low(v,r) ((v)->arch.ctxt.cp15[((r) + 1)]) +#else +#define vcpu_cp15_64_low(v,r) ((v)->arch.ctxt.cp15[((r) + 0)]) +#endif + struct kvm_vm_stat { u32 remote_tlb_flush; }; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8e65e31..a5aa1d1 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -134,12 +134,10 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, BUG_ON(!p->is_write); val = *vcpu_reg(vcpu, p->Rt); - if (!p->is_aarch32) { + if (!p->is_aarch32 || !p->is_32bit) { vcpu_sys_reg(vcpu, r->reg) = val; } else { - vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL; - if (!p->is_32bit) - vcpu_cp15(vcpu, r->reg + 1) = val >> 32; + vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL; } return true; }