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[91.189.95.16]) by mx.google.com with ESMTP id g48si1056664wee.27.2012.03.21.01.59.56; Wed, 21 Mar 2012 01:59:58 -0700 (PDT) Received-SPF: neutral (google.com: 91.189.95.16 is neither permitted nor denied by best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org) client-ip=91.189.95.16; Authentication-Results: mx.google.com; spf=neutral (google.com: 91.189.95.16 is neither permitted nor denied by best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org) smtp.mail=linaro-mm-sig-bounces@lists.linaro.org Received: from localhost ([127.0.0.1] helo=mombin.canonical.com) by mombin.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1SAHOb-0004eE-1G; Wed, 21 Mar 2012 08:59:53 +0000 Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]) by mombin.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1SAHOZ-0004dM-R6 for linaro-mm-sig@lists.linaro.org; Wed, 21 Mar 2012 08:59:51 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKT2mYh+wg0Kb+LTp6K0IMOjV43FhUyAdD@postini.com; Wed, 21 Mar 2012 08:59:51 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AB02A116; Wed, 21 Mar 2012 08:59:50 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5939B1A74; Wed, 21 Mar 2012 08:59:50 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 7580024C080; Wed, 21 Mar 2012 09:59:45 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 21 Mar 2012 09:59:49 +0100 From: To: Date: Wed, 21 Mar 2012 10:09:22 +0100 Message-ID: <1332320963-29001-4-git-send-email-benjamin.gaignard@stericsson.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1332320963-29001-1-git-send-email-benjamin.gaignard@stericsson.com> References: <1332320963-29001-1-git-send-email-benjamin.gaignard@stericsson.com> MIME-Version: 1.0 Subject: [Linaro-mm-sig] [PATCH v4 3/4] add CMA heap X-BeenThere: linaro-mm-sig@lists.linaro.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "Unified memory management interest group." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linaro-mm-sig-bounces@lists.linaro.org Errors-To: linaro-mm-sig-bounces@lists.linaro.org X-Gm-Message-State: ALoCoQnlP8JZ2UB15wNjfpsKi0HwyLWTUB91jFrJpP8bwQu+VBiC/fm4akzAFUQJeS5mIwZKXfDR From: Benjamin Gaignard New heap type ION_HEAP_TYPE_DMA where allocation is done with dma_alloc_coherent API. device coherent_dma_mask must be set to DMA_BIT_MASK(32). Add ion_heap_create_full function to avoid breaking backward compatibilty. Signed-off-by: Benjamin Gaignard --- drivers/gpu/ion/Makefile | 3 +- drivers/gpu/ion/ion_cma_heap.c | 129 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/ion/ion_heap.c | 14 ++++- drivers/gpu/ion/ion_priv.h | 9 +++ include/linux/ion.h | 3 + 5 files changed, 156 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/ion/ion_cma_heap.c diff --git a/drivers/gpu/ion/Makefile b/drivers/gpu/ion/Makefile index 73fe3fa..ddcedb5 100644 --- a/drivers/gpu/ion/Makefile +++ b/drivers/gpu/ion/Makefile @@ -1,2 +1,3 @@ -obj-$(CONFIG_ION) += ion.o ion_heap.o ion_system_heap.o ion_carveout_heap.o +ion-driver-objs += ion.o ion_heap.o ion_system_heap.o ion_carveout_heap.o ion_cma_heap.o +obj-$(CONFIG_ION) += ion-driver.o obj-$(CONFIG_ION_TEGRA) += tegra/ diff --git a/drivers/gpu/ion/ion_cma_heap.c b/drivers/gpu/ion/ion_cma_heap.c new file mode 100644 index 0000000..0dee6f0 --- /dev/null +++ b/drivers/gpu/ion/ion_cma_heap.c @@ -0,0 +1,129 @@ +/* + * drivers/gpu/ion/ion_cma_heap.c + * + * Copyright (C) Linaro 2012 + * Author: for ST-Ericsson. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +/* for ion_heap_ops structure */ +#include "ion_priv.h" + +#define ION_CMA_ALLOCATE_FAILED -1 + +struct ion_cma_buffer_info { + void *cpu_addr; + dma_addr_t handle; +}; + +/* ION CMA heap operations functions */ +static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer, + unsigned long len, unsigned long align, + unsigned long flags) +{ + struct device *dev = heap->priv; + struct ion_cma_buffer_info *info; + + dev_dbg(dev, "Request buffer allocation len %ld\n", len); + + info = kzalloc(sizeof(struct ion_cma_buffer_info), GFP_KERNEL); + if (!info) { + dev_err(dev, "Can't allocate buffer info\n"); + return ION_CMA_ALLOCATE_FAILED; + } + + info->cpu_addr = dma_alloc_coherent(dev, len, &(info->handle), 0); + + if (!info->cpu_addr) { + dev_err(dev, "Fail to allocate buffer\n"); + kfree(info); + return ION_CMA_ALLOCATE_FAILED; + } + + /* keep this for memory release */ + buffer->priv_virt = info; + dev_dbg(dev, "Allocate buffer %p\n", buffer); + return 0; +} + +static void ion_cma_free(struct ion_buffer *buffer) +{ + struct device *dev = buffer->heap->priv; + struct ion_cma_buffer_info *info = buffer->priv_virt; + + dev_dbg(dev, "Release buffer %p\n", buffer); + dma_free_coherent(dev, buffer->size, info->cpu_addr, info->handle); + kfree(info); +} + +/* return physical address in addr */ +static int ion_cma_phys(struct ion_heap *heap, struct ion_buffer *buffer, + ion_phys_addr_t *addr, size_t *len) +{ + struct device *dev = heap->priv; + struct ion_cma_buffer_info *info = buffer->priv_virt; + + dev_dbg(dev, "Return buffer %p physical address 0x%x\n", buffer, + virt_to_phys(info->cpu_addr)); + + *addr = virt_to_phys(info->cpu_addr); + *len = buffer->size; + + return 0; +} + +static int ion_cma_mmap(struct ion_heap *mapper, struct ion_buffer *buffer, + struct vm_area_struct *vma) +{ + struct device *dev = buffer->heap->priv; + struct ion_cma_buffer_info *info = buffer->priv_virt; + + return dma_mmap_coherent(dev, vma, info->cpu_addr, info->handle, + buffer->size); +} + +static struct ion_heap_ops ion_cma_ops = { + .allocate = ion_cma_allocate, + .free = ion_cma_free, + .phys = ion_cma_phys, + .map_user = ion_cma_mmap, +}; + +struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *data, + struct device *dev) +{ + struct ion_heap *heap; + + heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL); + + if (!heap) + return ERR_PTR(-ENOMEM); + + heap->ops = &ion_cma_ops; + /* set device as private heaps data, later it will be + * used to make the link with reserved CMA memory */ + heap->priv = dev; + heap->type = ION_HEAP_TYPE_DMA; + return heap; +} + +void ion_cma_heap_destroy(struct ion_heap *heap) +{ + kfree(heap); +} diff --git a/drivers/gpu/ion/ion_heap.c b/drivers/gpu/ion/ion_heap.c index 8ce3c19..7f5f325 100644 --- a/drivers/gpu/ion/ion_heap.c +++ b/drivers/gpu/ion/ion_heap.c @@ -18,7 +18,8 @@ #include #include "ion_priv.h" -struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data) +struct ion_heap *ion_heap_create_full(struct ion_platform_heap *heap_data, + struct device *dev) { struct ion_heap *heap = NULL; @@ -32,6 +33,9 @@ struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data) case ION_HEAP_TYPE_CARVEOUT: heap = ion_carveout_heap_create(heap_data); break; + case ION_HEAP_TYPE_DMA: + heap = ion_cma_heap_create(heap_data, dev); + break; default: pr_err("%s: Invalid heap type %d\n", __func__, heap_data->type); @@ -50,6 +54,11 @@ struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data) return heap; } +struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data) +{ + return ion_heap_create_full(heap_data, NULL); +} + void ion_heap_destroy(struct ion_heap *heap) { if (!heap) @@ -65,6 +74,9 @@ void ion_heap_destroy(struct ion_heap *heap) case ION_HEAP_TYPE_CARVEOUT: ion_carveout_heap_destroy(heap); break; + case ION_HEAP_TYPE_DMA: + ion_cma_heap_destroy(heap); + break; default: pr_err("%s: Invalid heap type %d\n", __func__, heap->type); diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h index bf5c75e..7607b26 100644 --- a/drivers/gpu/ion/ion_priv.h +++ b/drivers/gpu/ion/ion_priv.h @@ -22,6 +22,7 @@ #include #include #include +#include struct ion_mapping; @@ -159,6 +160,9 @@ void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap); */ struct ion_heap *ion_heap_create(struct ion_platform_heap *); +struct ion_heap *ion_heap_create_full(struct ion_platform_heap *, + struct device *); + void ion_heap_destroy(struct ion_heap *); struct ion_heap *ion_system_heap_create(struct ion_platform_heap *); @@ -177,6 +181,11 @@ ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap, unsigned long size, unsigned long align); void ion_carveout_free(struct ion_heap *heap, ion_phys_addr_t addr, unsigned long size); + +struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *, + struct device *); +void ion_cma_heap_destroy(struct ion_heap *); + /** * The carveout heap returns physical addresses, since 0 may be a valid * physical address, this is used to indicate allocation failed diff --git a/include/linux/ion.h b/include/linux/ion.h index 1468cb3..5104e64 100644 --- a/include/linux/ion.h +++ b/include/linux/ion.h @@ -27,12 +27,14 @@ struct ion_handle; * @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved * carveout heap, allocations are physically * contiguous + * @ION_HEAP_TYPE_DMA: memory allocated via DMA API * @ION_HEAP_END: helper for iterating over heaps */ enum ion_heap_type { ION_HEAP_TYPE_SYSTEM, ION_HEAP_TYPE_SYSTEM_CONTIG, ION_HEAP_TYPE_CARVEOUT, + ION_HEAP_TYPE_DMA, ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always are at the end of this enum */ ION_NUM_HEAPS, @@ -41,6 +43,7 @@ enum ion_heap_type { #define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM) #define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG) #define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT) +#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA) #ifdef __KERNEL__ struct ion_device;