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[54.225.227.206]) by mx.google.com with ESMTPS id hj6si11061610wjb.37.2013.06.19.22.50.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 19 Jun 2013 22:50:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Received: from localhost ([127.0.0.1] helo=ip-10-141-164-156.ec2.internal) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1UpXkz-0002B9-De; Thu, 20 Jun 2013 05:50:05 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1UpXkx-0002AV-EH for linaro-mm-sig@lists.linaro.org; Thu, 20 Jun 2013 05:50:03 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 19 Jun 2013 22:50:13 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 19 Jun 2013 22:49:58 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 19 Jun 2013 22:49:58 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Wed, 19 Jun 2013 22:49:58 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 19 Jun 2013 22:49:57 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5K5nodc013397; Wed, 19 Jun 2013 22:49:56 -0700 (PDT) From: Hiroshi Doyu To: , Date: Thu, 20 Jun 2013 08:49:43 +0300 Message-ID: <1371707384-30037-3-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1371707384-30037-1-git-send-email-hdoyu@nvidia.com> References: <1371707384-30037-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Cc: linux-tegra@vger.kernel.org, linaro-mm-sig@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: [Linaro-mm-sig] [RFC 2/3] ARM: dma-mapping: Pass DMA attrs as IOMMU prot X-BeenThere: linaro-mm-sig@lists.linaro.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: linaro-mm-sig-bounces@lists.linaro.org Sender: linaro-mm-sig-bounces@lists.linaro.org X-Gm-Message-State: ALoCoQlXo/jBhNpaCDb4uuTi7iZIBNHaLIWGNukjKJzmf8ehhXK5V62TJI9N0j24A5KDyYkwgck5 X-Original-Sender: hdoyu@nvidia.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Pass DMA attribute as IOMMU property, which can be proccessed in the backend implementation of IOMMU. For example, DMA_ATTR_READ_ONLY can be translated into each IOMMU H/W implementaion. Signed-off-by: Hiroshi Doyu --- arch/arm/mm/dma-mapping.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4152ed6..cbc6768 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1254,7 +1254,8 @@ err: */ static dma_addr_t ____iommu_create_mapping(struct device *dev, dma_addr_t *req, - struct page **pages, size_t size) + struct page **pages, size_t size, + struct dma_attrs *attrs) { struct dma_iommu_mapping *mapping = dev->archdata.mapping; unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; @@ -1280,7 +1281,7 @@ ____iommu_create_mapping(struct device *dev, dma_addr_t *req, break; len = (j - i) << PAGE_SHIFT; - ret = iommu_map(mapping->domain, iova, phys, len, 0); + ret = iommu_map(mapping->domain, iova, phys, len, (int)attrs); if (ret < 0) goto fail; iova += len; @@ -1294,9 +1295,10 @@ fail: } static dma_addr_t -__iommu_create_mapping(struct device *dev, struct page **pages, size_t size) +__iommu_create_mapping(struct device *dev, struct page **pages, size_t size, + struct dma_attrs *attrs) { - return ____iommu_create_mapping(dev, NULL, pages, size); + return ____iommu_create_mapping(dev, NULL, pages, size, attrs); } static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) @@ -1332,7 +1334,7 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) } static void *__iommu_alloc_atomic(struct device *dev, size_t size, - dma_addr_t *handle) + dma_addr_t *handle, struct dma_attrs *attrs) { struct page *page; void *addr; @@ -1341,7 +1343,7 @@ static void *__iommu_alloc_atomic(struct device *dev, size_t size, if (!addr) return NULL; - *handle = __iommu_create_mapping(dev, &page, size); + *handle = __iommu_create_mapping(dev, &page, size, attrs); if (*handle == DMA_ERROR_CODE) goto err_mapping; @@ -1378,17 +1380,20 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, size = PAGE_ALIGN(size); if (gfp & GFP_ATOMIC) - return __iommu_alloc_atomic(dev, size, handle); + + return __iommu_alloc_atomic(dev, size, handle, attrs); pages = __iommu_alloc_buffer(dev, size, gfp); if (!pages) return NULL; if (*handle == DMA_ERROR_CODE) - *handle = __iommu_create_mapping(dev, pages, size); + *handle = __iommu_create_mapping(dev, pages, size, attrs); else - *handle = ____iommu_create_mapping(dev, handle, pages, size); + *handle = ____iommu_create_mapping(dev, handle, pages, size, + attrs); + *handle = __iommu_create_mapping(dev, pages, size, attrs); if (*handle == DMA_ERROR_CODE) goto err_buffer; @@ -1513,7 +1518,7 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, skip_cmaint: count = size >> PAGE_SHIFT; - ret = iommu_map_sg(mapping->domain, iova_base, sg, count, 0); + ret = iommu_map_sg(mapping->domain, iova_base, sg, count, (int)attrs); if (WARN_ON(ret < 0)) goto fail; @@ -1716,7 +1721,8 @@ static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *p if (dma_addr == DMA_ERROR_CODE) return dma_addr; - ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); + ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, + (int)attrs); if (ret < 0) goto fail; @@ -1756,7 +1762,8 @@ static dma_addr_t arm_iommu_map_page_at(struct device *dev, struct page *page, if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) __dma_page_cpu_to_dev(page, offset, size, dir); - ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); + ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, + (int)attrs); if (ret < 0) return DMA_ERROR_CODE; @@ -1778,7 +1785,8 @@ static dma_addr_t arm_iommu_map_pages(struct device *dev, struct page **pages, __dma_page_cpu_to_dev(pages[i], 0, PAGE_SIZE, dir); } - ret = iommu_map_pages(mapping->domain, dma_handle, pages, count, 0); + ret = iommu_map_pages(mapping->domain, dma_handle, pages, count, + (int)attrs); if (ret < 0) return DMA_ERROR_CODE;