From patchwork Tue Jun 13 11:48:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105152 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp362130qgd; Tue, 13 Jun 2017 04:50:08 -0700 (PDT) X-Received: by 10.99.109.143 with SMTP id i137mr45049452pgc.62.1497354608609; Tue, 13 Jun 2017 04:50:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497354608; cv=none; d=google.com; s=arc-20160816; b=EIumasJ8+Vybq47Yqfqbs58z2v2oOtqK3l+lVUK5k8YkBpezYxK9ph82TQLB+vzd4Q doj7NYPzA/5JG8tg8AKJ0+cyLLqS8CqIWALGWSKYQxT9srF9up0ckoaxewe3lmsTMBVE ugFDY82E9KP+n0Wi7SIpmCVtxo5xdqq0GApHRlmILEnIP3HJ8GtkVDqMjYTxevlsqfKq 0/t9aFJDEVoSxM6+qV3vQSi6nMIHFbgP+8AVsjqBPgzHYpn3KU1rvHp2YTTMo05ZQC0a JRYEmIMlT+h/MmA0gYZl2v+c4CZb7Cjf4mz5tHydGzP8UYqAYJzZQGbIf12kq8b03Izd eKkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=q8A0FgGhPHsvoc85rg8AGXhIVpWXGZLlKK559li+HkQ=; b=BHQ48kB7ZlTT6QNqNDRWYbI4RJOnmHsPNr6ViKEfCGIM6k4vV9Twjq5WZpGUp2i+43 Ueu8Cg3gPxub6oIycea0VkdKaPH8MCWvHHvohi6FRnlQU4BZUY6MQm+UfP9vwznq9Mua PjZInYoBrXSroe0dQ8O3Z7ttczCXhjJb75FF97aP+0cW2PrlxVbDQGhcawsj8j1xH81P AU/e54/8f0tVW5VH2jkA0PZmO2OClLVU3tOjoOzloVwF7Jz8ukmqtSzh37Oinq5tlqg/ nKQ5rO04LlzYN/ijajL4BBpxhSM64+vFAEaJcxJKGBhPYNkhT5xgiigYmqxXE0dKvAOi +1LA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z73si9570643plh.548.2017.06.13.04.50.08; Tue, 13 Jun 2017 04:50:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753224AbdFMLuB (ORCPT + 8 others); Tue, 13 Jun 2017 07:50:01 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8272 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753128AbdFMLuA (ORCPT ); Tue, 13 Jun 2017 07:50:00 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQF82945; Tue, 13 Jun 2017 19:49:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Tue, 13 Jun 2017 19:49:43 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH 0/2] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Tue, 13 Jun 2017 12:48:27 +0100 Message-ID: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.593FD162.010E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fe6a51a63f900b64b1a315831bb79592 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve and reserve the HW ITS address regions. 2. Added quirk to SMMUv3 to reserve HW ITS address regions based on IORT SMMUv3 model. This is based on the following patches: 1. https://patchwork.kernel.org/patch/9740733/ 2. https://patchwork.kernel.org/patch/9730491/ Thanks, Shameer RFCv2 -->PATCH Incorporated Lorenzo's review comments. RFC v1 -->v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. shameer (2): acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 drivers/acpi/arm64/iort.c | 92 ++++++++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu-v3.c | 27 +++++++++--- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 4 files changed, 119 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html