@@ -523,6 +523,81 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata)
#endif
}
+/*
+ * arm_err_trans_type_to_acpi_cache_type: Function to convert transaction type
+ * in the CPER's ARM cache error structure to the ACPI PPTT cache type.
+ *
+ * @type - transaction type. Type of cache error instruction/data/generic.
+ *
+ * Return: Success: ACPI PPTT cache type. Failure: Negative value.
+ */
+static u8 arm_err_trans_type_to_acpi_cache_type(u8 type)
+{
+ switch (type) {
+ case CPER_ARM_CACHE_TRANS_TYPE_INSTRUCTION:
+ return ACPI_PPTT_CACHE_TYPE_INSTR;
+ case CPER_ARM_CACHE_TRANS_TYPE_DATA:
+ return ACPI_PPTT_CACHE_TYPE_DATA;
+ case CPER_ARM_CACHE_TRANS_TYPE_GENERIC:
+ return ACPI_PPTT_CACHE_TYPE_UNIFIED;
+ default:
+ pr_warn_ratelimited("FW_WARN GHES_PFX ARM CPER: Invalid cache transaction type\n");
+ return -EINVAL;
+ }
+}
+
+static void ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata)
+{
+ struct cper_sec_proc_arm *error = acpi_hest_get_payload(gdata);
+ struct cper_arm_err_info *err_info;
+ struct ghes_einfo_cpu einfo;
+ u8 trans_type;
+ u64 error_info;
+ int sec_sev;
+ int i, cache_type;
+
+ log_arm_hw_error(error);
+
+ sec_sev = ghes_severity(gdata->error_severity);
+
+#if defined(CONFIG_ARM64)
+ if (sec_sev == GHES_SEV_CORRECTED) {
+ memset(&einfo, 0, sizeof(einfo));
+ einfo.cpu = get_logical_index(error->mpidr);
+ if (einfo.cpu == -EINVAL)
+ return;
+
+ /* ARM processor error types are cache/TLB/bus errors.
+ * Presently corrected error count for caches only
+ * is reported.
+ */
+ err_info = (struct cper_arm_err_info *)(error + 1);
+
+ for (i = 0; i < error->err_info_num; i++) {
+ if (err_info->type != CPER_ARM_CACHE_ERROR)
+ continue;
+ einfo.ce_count = err_info->multiple_error + 1;
+
+ error_info = err_info->error_info;
+ if (!(error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) ||
+ !(error_info & CPER_ARM_ERR_VALID_LEVEL))
+ continue;
+
+ trans_type = ((error_info >> CPER_ARM_ERR_TRANSACTION_SHIFT)
+ & CPER_ARM_ERR_TRANSACTION_MASK);
+ cache_type = arm_err_trans_type_to_acpi_cache_type(trans_type);
+ if (cache_type < 0)
+ continue;
+ einfo.cache_type = cache_type;
+ einfo.cache_level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT)
+ & CPER_ARM_ERR_LEVEL_MASK);
+ ghes_edac_report_cpu_error(&einfo);
+ err_info += 1;
+ }
+ }
+#endif
+}
+
static BLOCKING_NOTIFIER_HEAD(vendor_record_notify_list);
int ghes_register_vendor_record_notifier(struct notifier_block *nb)
@@ -605,9 +680,7 @@ static bool ghes_do_proc(struct ghes *ghes,
ghes_handle_aer(gdata);
}
else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
- struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);
-
- log_arm_hw_error(err);
+ ghes_handle_arm_hw_error(gdata);
} else {
void *err = acpi_hest_get_payload(gdata);
@@ -314,6 +314,10 @@ enum {
#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
+#define CPER_ARM_CACHE_TRANS_TYPE_INSTRUCTION 0
+#define CPER_ARM_CACHE_TRANS_TYPE_DATA 1
+#define CPER_ARM_CACHE_TRANS_TYPE_GENERIC 2
+
/*
* All tables and structs must be byte-packed to match CPER
* specification, since the tables are provided by the system BIOS