From patchwork Mon May 15 05:49:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 682003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D00C77B7D for ; Mon, 15 May 2023 05:55:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238961AbjEOFzk (ORCPT ); Mon, 15 May 2023 01:55:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233970AbjEOFyg (ORCPT ); Mon, 15 May 2023 01:54:36 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E144B2684 for ; Sun, 14 May 2023 22:51:34 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1aad55244b7so93709435ad.2 for ; Sun, 14 May 2023 22:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684129893; x=1686721893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IS1GWILYl7Q6QsdApEh939z6h09NwhOHpvU6XTgdfRk=; b=csvVea0/Upvs+e/kvOVx0v5vn2HOJORQbM6M+e03WFd3D+jy/1h0Jc4uWPHETq7pAi B2oxN+0/NcooJYNHOQK6y8pTg2ObPZr1tTH7inBU+XHT6em5CA9TUr/0eC7DErUXZPjJ mTEVurLQslXQBtarT2oOyzq/yvIZe0/k/gXwbWXt2bNeLsM3uUwJJ7OXM7DFBREwFdpy Spcr/xd6W2ShZz9ZW66OO+BhLP/ouyjgjSeHqhszfiVrK1dz2JaSLRg8V8x3VDtUgWkt IisUCX07oJ+0INM7uMStg3kzoXfhqM+EiG4lFoF199+PXntlyPkl4XG0PAnHWf2JhW+U p6sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684129893; x=1686721893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IS1GWILYl7Q6QsdApEh939z6h09NwhOHpvU6XTgdfRk=; b=bVXAcriQaCVvs9feOO1qVNb9C8R3jv9Fo2WIV5iXHnXQAULSOMd1N98WpzqLHXIBJy OVFEKWITDfKATkO4/dPivko6wS8LR/zaoNOld6yWBlxymBNQGow5mZMpkyWu8MiIdq5W Smk88VP/FtT5Es+Q7uE7FAA0AizsFE987Bx2n0QUpCD8BTp4EqkTSOJGBAnc4osuDX66 q5dLCInXX3byFCmepRpe6Kf6QZ5Z69HJc3XyWyvqPxG9+G9PxRgrEx1L7XWCaSQvfn8Z bHiiBuIkRJ99RvVRHPyMqwf4piMAmbU/a+MZVsVrJGO4b94Ciq1WK6lDlJlL9/3vb94R 6h6g== X-Gm-Message-State: AC+VfDw2LAxRAyT7Dn8+KPlVz3zbFx6uDy/Nd6fEbaax4yjMD3KraVJp 7fffxeliN70aDhAgBDPiKt71YQ== X-Google-Smtp-Source: ACHHUZ7buSle7e6BYrW3/obLZDohFRy8Vxc6R0Jdryndp9BmcFr7gna75GEfGN/V2L/t/8Mcx129kg== X-Received: by 2002:a17:902:ee89:b0:1a6:74f6:fa92 with SMTP id a9-20020a170902ee8900b001a674f6fa92mr35025309pld.19.1684129893096; Sun, 14 May 2023 22:51:33 -0700 (PDT) Received: from localhost.localdomain ([106.51.191.118]) by smtp.gmail.com with ESMTPSA id f10-20020a17090274ca00b001ab28f620d0sm12423277plt.290.2023.05.14.22.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 May 2023 22:51:32 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Sunil V L , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Anup Patel , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V6 17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Date: Mon, 15 May 2023 11:19:24 +0530 Message-Id: <20230515054928.2079268-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com> References: <20230515054928.2079268-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Refactor the timer init function such that few things can be shared by both DT and ACPI based platforms. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 81 +++++++++++++++---------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..cecc4662293b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init riscv_timer_init_dt(struct device_node *n) +static int __init riscv_timer_init_common(void) { - int cpuid, error; - unsigned long hartid; - struct device_node *child; + int error; struct irq_domain *domain; + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); - error = riscv_of_processor_hartid(n, &hartid); - if (error < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); - return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) - return 0; - - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); - if (child) { - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, - "riscv,timer-cannot-wake-cpu"); - of_node_put(child); - } - - domain = NULL; - child = of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain = irq_find_host(child); - of_node_put(child); + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); if (!domain) { - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", + intc_fwnode); return -ENODEV; } riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); if (!riscv_clock_event_irq) { - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("RISCV timer registration failed [%d]\n", error); return error; } @@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n) return error; } +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, error; + unsigned long hartid; + struct device_node *child; + + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", + n, hartid); + return error; + } + + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); + return cpuid; + } + + if (cpuid != smp_processor_id()) + return 0; + + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + + return riscv_timer_init_common(); +} + TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);