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Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v3 1/5] x86/cpufeatures: Rename X86_FEATURE_FAST_CPPC to have AMD prefix Date: Wed, 23 Oct 2024 12:43:53 -0500 Message-ID: <20241023174357.34338-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023174357.34338-1-mario.limonciello@amd.com> References: <20241023174357.34338-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|DS0PR12MB7653:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b6951b2-e04d-490b-bccb-08dcf38a5f4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: PiBO8dxAtbVEs95BYz+4D2OfwOKmPXbPMXDCATSetxwY0p43XU6NBdrX8Ab9S8i8FlL/5C5yTvBRCn0j/IK8E/HKmfmYnLx0S0FEBBlaYO2U7Dq0Se+OD5M/HGs0mhMiEQbDJSjN1U2bErpE0LhLJCObqm0hJRYM7KsO0282GuF3aCwdEM5c1A16NndbZCpkgZuyHOHlDhiqQRK1KTywmFeioPK30WyQLoXGa/vdCFOwmvOc0oXBQGBrUMCDzS6Jz0GhP6qsmWaWchtuDafv8rFNsO/SnaEJy+tFeZ68pXnGtrDzeW5DE/zRD9L1IpCHTresDWqbJsO3fs2kS6T+YXdoEmW7ur+l+0Mv+/jYqAtxSREKv0++bWxMoxvuZK6b33CsuuIOuiu512yklyakMhS806nxwCs0BVhUj9MXv66Rv79SJjncOqCyhLTfyq/36XHoLrtFMGNMTftpKw894hMh3amfZMwZQKu7ZSBr1TuotKwqBG0lQamQrC1Q+xLunH/GysqRIBtKWycEu4h11SqQSUKOR0Eqnei+4Tl7aVmX84Bdm8hs7Lk+2rrRAamXY5tXEh9Z6IRI6prQQbRi1Utkk8EUGe/auTefhiRCmLjkh/49+UW1JeRMpmZyH3ZJbmhzHW89K1AXn8IKf4yaXyZ0HHQ/HyNp0jkR9dzMUZsCqAQsOO352N4kxh6FItPMw4G+Xcio8a4aL0yJCbvP7MSNzQus8K2e+TsqoC3S8fAhTgbgnHJ+13Ul+NQsvdCtFWnVdEMQv7lNVQmPt/bLMBRmY2UzeL+ycUxhoC7A6qoZkwM5rbQFI4oWta8z2AnzdVFHPeXJ+mbalSps/cH81DqBs+h6FPcXrIZFEY2KxOjhsYm02BlFvEreeDjI8kS75xmMDy3IPHKWUPv1yUBl5wcp+5vrCX3EAVPH6Om8+QiQipO4KQ4E7lT6JEsHqI1xcmiIBttDKCl77NC0QMg47Kl/i5FVVj6Ats5Kr/aPWCqRvCu1gUr6nQkrp3Rga4a0WW3iUd7w6DhHU+ns0FCVydXZCMU6CyFsBhJ3a6CV1fqC/VpnW5UKGRhraYdFsSLk3Dl6o7rEJv6jbvY/NFzw3/p09sBIzCFqcDBap7b4PvgUIB1xwIqdd5FAnkVmnhuWmBHEG6HtE+dAjLP/mBxW86pRL88WOK0PLJ/vOYXB/i8C83mXrRLJBWomVjg3MfE0e9TKloEM88V+0TbR/ag64ZxRCZri2GoeCtusvIFBqzBrsshspyjTnoiTUI5fxCSAqypiEK5SKzlN5fljG01jp58KM7vmq17RomJyO54EfbprEr1CqKoO++VxB3MeOKQN9n4vtjpeAcb8+UH4zDXndol2sd1kv5+E//NmgxuuSQo3SZKWzTxel2++eJKfcLTGXI5IbaLVGnbrnljxWNhc+g== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:44:40.8146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b6951b2-e04d-490b-bccb-08dcf38a5f4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7653 This feature is an AMD unique feature of some processors, so put AMD into the name. Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 2 +- drivers/cpufreq/amd-pstate.c | 2 +- tools/arch/x86/include/asm/cpufeatures.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 913fd3a7bac65..aa63437a677c0 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -473,7 +473,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index c84c30188fdf2..1db2bb81a3847 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,7 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, - { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b63863f77c677..717b4cf4d9c4c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -847,7 +847,7 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) transition_delay_ns = cppc_get_transition_latency(cpu); if (transition_delay_ns == CPUFREQ_ETERNAL) { - if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC)) return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; else return AMD_PSTATE_TRANSITION_DELAY; diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index dd4682857c120..23698d0f4bb47 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -472,7 +472,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ /* * BUG word(s)