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Thu, 5 Dec 2024 21:19:19 +0000 From: Zaid Alali To: rafael@kernel.org, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, bp@alien8.de, robert.moore@intel.com, dan.j.williams@intel.com, zaidal@os.amperecomputing.com, Jonathan.Cameron@huawei.com, Benjamin.Cheatham@amd.com, Avadhut.Naik@amd.com, viro@zeniv.linux.org.uk, arnd@arndb.de, ira.weiny@intel.com, dave.jiang@intel.com, sthanneeru.opensrc@micron.com, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, acpica-devel@lists.linux.dev Subject: [PATCH v2 9/9] ACPI: APEI: EINJ: Update the documentation for EINJv2 support Date: Thu, 5 Dec 2024 13:18:54 -0800 Message-Id: <20241205211854.43215-10-zaidal@os.amperecomputing.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205211854.43215-1-zaidal@os.amperecomputing.com> References: <20241205211854.43215-1-zaidal@os.amperecomputing.com> X-ClientProxiedBy: MW4PR04CA0126.namprd04.prod.outlook.com (2603:10b6:303:84::11) To SN7PR01MB7903.prod.exchangelabs.com (2603:10b6:806:34f::17) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN7PR01MB7903:EE_|DS7PR01MB7759:EE_ X-MS-Office365-Filtering-Correlation-Id: 7c0af457-df1d-4872-aeb0-08dd15727adf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Bit 1 - Memory address and mask valid (param1 and param2). + Memory address and range valid (param1 and param2). Bit 2 PCIe (seg,bus,dev,fn) valid (see param4 below). + Bit 3 + EINJv2 extension structure is valid If set to zero, legacy behavior is mimicked where the type of injection specifies just one bit set, and param1 is multiplexed. @@ -110,6 +115,7 @@ The following files belong to it: Used when the 0x1 bit is set in "flags" to specify the APIC id - param4 + Used when the 0x4 bit is set in "flags" to specify target PCIe device - notrigger @@ -122,6 +128,18 @@ The following files belong to it: this actually works depends on what operations the BIOS actually includes in the trigger phase. +- einjv2_component_count + + The value from this file is used to set the "Component Array Count" + field of EINJv2 Extension Structure. + +- einjv2_component_array + + The contents of this file are used to set the "Component Array" field + of the EINJv2 Extension Structure. The expected format is hex values + for component id and syndrome separated by space, and multiple + components are separated by new line. + CXL error types are supported from ACPI 6.5 onwards (given a CXL port is present). The EINJ user interface for CXL error types is at /cxl. The following files belong to it: @@ -139,7 +157,6 @@ is present). The EINJ user interface for CXL error types is at under /apei/einj, while CXL 1.1/1.0 port injections must use this file. - BIOS versions based on the ACPI 4.0 specification have limited options in controlling where the errors are injected. Your BIOS may support an extension (enabled with the param_extension=1 module parameter, or boot @@ -194,6 +211,26 @@ An error injection example:: # echo 0x8 > error_type # Choose correctable memory error # echo 1 > error_inject # Inject now +An EINJv2 error injection example:: + + # cd /sys/kernel/debug/apei/einj + # cat available_error_type # See which errors can be injected + 0x00000002 Processor Uncorrectable non-fatal + 0x00000008 Memory Correctable + 0x00000010 Memory Uncorrectable non-fatal + 0x00000001 EINJV2 Processor Error + 0x00000002 EINJV2 Memory Error + + # echo 0x12345000 > param1 # Set memory address for injection + # echo 0xfffffffffffff000 > param2 # Range - anywhere in this page + # comp_arr="0x1 0x2 # Fill in the component array + >0x1 0x4 + >0x2 0x4" + # echo "$comp_arr" > einjv2_component_array + # echo 0x2 > error_type # Choose EINJv2 memory error + # echo 0xa > flags # set flags to indicate EINJv2 + # echo 1 > error_inject # Inject now + You should see something like this in dmesg:: [22715.830801] EDAC sbridge MC3: HANDLING MCE MEMORY ERROR