From patchwork Mon Apr 7 02:05:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 878724 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [61.152.208.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2AB2213221 for ; Mon, 7 Apr 2025 02:07:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=61.152.208.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743991648; cv=none; b=hCIzLti5ak/432JxCHDlwEiFMAzKmtogD9xFmD6eW/RT3VrYvBQ+Yd5gP8DzwiZad0uzcPFUM/VxDThY20q5R8NcX4nyCCQckt6eG4qp5WzwHWpgwPDmxK3Oxu8XBYneo7EEFgkUnSLrErtLVmv7r9vtk5qrFpu9OvzmGI+RKr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743991648; c=relaxed/simple; bh=MGi4qtb6SLMs94x+IvcEx7bVKqBnqXah0fRCJh5j1lM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hGqYLumSs1bpYHjXI29Nb4A11gRknA3r9+9+bdGUWTc9CdI5SUDG1vYrCDE4MA3tpFXJ++kQhT2BBH0B/zqBpqkRJYCwX8bqxLDsKiE/PTQsII/u3B748dFZUrNyjSTMekN/Azx743ZuLt4oFO8uhiT7YyixTyZHvoD0UKgF5hU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=61.152.208.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1743991642-1eb14e119e07000001-I98ny2 Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx2.zhaoxin.com with ESMTP id vIuMEgiPZyEdy58z (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 07 Apr 2025 10:07:22 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXSHMBX3.zhaoxin.com (10.28.252.165) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.44; Mon, 7 Apr 2025 10:07:22 +0800 Received: from ZXSHMBX3.zhaoxin.com ([fe80::8cc5:5bc6:24ec:65f2]) by ZXSHMBX3.zhaoxin.com ([fe80::8cc5:5bc6:24ec:65f2%6]) with mapi id 15.01.2507.044; Mon, 7 Apr 2025 10:07:22 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 7 Apr 2025 10:06:04 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v6 4/4] PCI: ACPI: Add new pci_acpi_program_hest_aer_params() Date: Mon, 7 Apr 2025 10:05:57 +0800 X-ASG-Orig-Subj: [PATCH v6 4/4] PCI: ACPI: Add new pci_acpi_program_hest_aer_params() Message-ID: <20250407020557.1225166-5-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250407020557.1225166-1-LeoLiu-oc@zhaoxin.com> References: <20250407020557.1225166-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 4/7/2025 10:07:21 AM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1743991642 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5073 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.139598 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Call the func pci_acpi_program_hest_aer_params() for every PCIe device, the purpose of this function is to extract register value from HEST PCIe AER structures and program them into AER Capabilities. This function applies to all hardware platforms that has a PCI Express AER structure in HEST. Signed-off-by: LeoLiuoc --- drivers/pci/pci-acpi.c | 88 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 6 +++ drivers/pci/probe.c | 1 + 3 files changed, 95 insertions(+) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index af370628e583..027057faca33 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "pci.h" /* @@ -806,6 +807,93 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) return -ENODEV; } +#ifdef CONFIG_ACPI_APEI +/* + * program_hest_aer_common() - configure AER common registers for Root Ports, + * Endpoints and PCIe to PCI/PCI-X bridges + */ +static void program_hest_aer_common(struct acpi_hest_aer_common aer_common, struct pci_dev *dev, + int pos) +{ + u32 uncor_mask = aer_common.uncorrectable_mask; + u32 uncor_severity = aer_common.uncorrectable_severity; + u32 cor_mask = aer_common.correctable_mask; + u32 adv_cap = aer_common.advanced_capabilities; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); +} + +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, struct pci_dev *dev, int pos) +{ + u32 root_err_cmd = aer_root->root_error_command; + + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); +} + +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; + u32 uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; + u32 adv_cap2 = hest_aer_bridge->advanced_capabilities2; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); +} + +static void program_hest_aer_params(struct hest_parse_aer_info info) +{ + struct pci_dev *dev; + int port_type; + int pos; + struct acpi_hest_aer_root *hest_aer_root; + struct acpi_hest_aer *hest_aer_endpoint; + struct acpi_hest_aer_bridge *hest_aer_bridge; + + dev = info.pci_dev; + port_type = pci_pcie_type(dev); + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + switch (port_type) { + case PCI_EXP_TYPE_ROOT_PORT: + hest_aer_root = (struct acpi_hest_aer_root *)info.data; + program_hest_aer_common(hest_aer_root->aer, dev, pos); + program_hest_aer_root(hest_aer_root, dev, pos); + break; + case PCI_EXP_TYPE_ENDPOINT: + hest_aer_endpoint = (struct acpi_hest_aer *)info.data; + program_hest_aer_common(hest_aer_endpoint->aer, dev, pos); + break; + case PCI_EXP_TYPE_PCI_BRIDGE: + hest_aer_bridge = (struct acpi_hest_aer_bridge *)info.data; + program_hest_aer_common(hest_aer_bridge->aer, dev, pos); + program_hest_aer_bridge(hest_aer_bridge, dev, pos); + break; + default: + break; + } +} + +void pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + struct hest_parse_aer_info info = { + .pci_dev = dev + }; + + if (!pci_is_pcie(dev)) + return; + + if (apei_hest_parse(hest_parse_pcie_aer, &info) > 0) + program_hest_aer_params(info); +} +#endif + /** * pciehp_is_native - Check whether a hotplug port is handled by the OS * @bridge: Hotplug port to check diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62..46af751878f5 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -977,6 +977,12 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } #endif +#ifdef CONFIG_ACPI_APEI +void pci_acpi_program_hest_aer_params(struct pci_dev *dev); +#else +static inline void pci_acpi_program_hest_aer_params(struct pci_dev *dev) { } +#endif + #ifdef CONFIG_ACPI bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); int pci_acpi_program_hp_params(struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 364fa2a514f8..77477a9a7d83 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2366,6 +2366,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_serr(dev); pci_acpi_program_hp_params(dev); + pci_acpi_program_hest_aer_params(dev); } static void pci_release_capabilities(struct pci_dev *dev)