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Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh Subject: [PATCH v4 08/12] iommu/arm-smmu-v3: Support IOMMU_VIOMMU_ALLOC Date: Wed, 30 Oct 2024 21:20:52 -0300 Message-ID: <8-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <0-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> References: X-ClientProxiedBy: BL1P223CA0023.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::28) To CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB8659:EE_|DM4PR12MB7573:EE_ X-MS-Office365-Filtering-Correlation-Id: 2163518a-4ab1-4c06-444d-08dcf941e402 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|366016|1800799024|921020; X-Microsoft-Antispam-Message-Info: bLfBIZ+V0JjfK0Oodefax4O9FxmkRvcyJtgiaZZNt+rE6qmRxlKFhx3ubHEvKkSCWI+25UnkBuThpo4QkNFJ3U6OwSWGXH7+ip6loAgwJHTR83ygqN6Sxda6ONPz/oUYLHfGXCLZIKkbGEQxfjkSFg5exmQde9336JiFGvwHeGzs+Cu6fgkofYDzfqPziL69K7aObbVwDcBtdusN6HXtgJkxhr4H/+hsFlnK2GFtYKOCv+elWQjCHox2srv3F7KO06oqBAnVXhATuIx8s75liWl2EKmHGEZN4o9AZwHe5vY9ZhNv0tdPI9y861DiCYIg2iwGpNTCzPDcOJqLScPyj8367tkxI4bMW8tkzWWNJIdaKOayvBG0obMTx++T6fRu138l37Ds3Sr4usBt8a54aY/zt4iqQVxuTabVP2c1OFFPGNNOaJibjwz5x0BGVFZxVu1KgEC6IcMSHVMDOp9CFDVQi808XKN/UqWMUioEkdcPaGM7mfp7qfe740KtJXXCMS5ZK9djIN6aqtFk0Q5WzVYagb5ZzSzV36GdLIMvPmBYRJlI80EoCJlnjhd01cE59jtjXwSlZcrHRcKSOwDlY2rMHMxL1SQCBs78O75Pvb7pPXt+MKTVOXnzfohJIdzQtioopm3ibrHTZXfbxR3/8rotjibDwkFK3BV5/oEiH7jY7LNndbPZ1zQmzPTeF5CBo2IrotL6wIvMk89L3OpJ+nxAi98pGf2Z55UsGG7FF0PDQXzhkYBWt4Kshm0QiWVhn/SuCQFX8ZY4+2yeQZWou8PHdQwpLL97GL33QXyGw/2vuevLDW3xcjSJb60BKVHC5iatSpOotU89i+GqaY8Ect2fD0/ktHxnPcfiXO22szDMWR/a8N5ZP6vVBEvUK630dDr6i3MiVmkE1FKkhiYjNCYmQW1z2G3nsHcnlRrA6wp9lFqf6aitGDXsl4LMlF76i3lx+c6MrezHfMMP4tC2ObP6k19h14a6B3E5x2zICXgsRaI6U5VqVhEktYfla69YVSEb41gXyUzQc3vQatdUgiGjLdYPXvNVkK3HB16ocmXXrcwdsTXTJo9F2IuzxmlV1Rt0u8/JfjpZnYVYFklxGJHO7G/7blMSMElvE175P+99SkZtz59cj0JUgf8Z2XAV6LgoRZSbT2B5dU94euitVgqO4VKB+hTcmiaEVfm1XpsFDQKmP5mX+ruokGM1BcJxmysYu2a+CI1W01fl9F8EuxyW2Umkmew/CvGjSvLASMkYfnk3mIOT5nPnRj10UOp7hAmaYw2ccjCH31x6wifvWemKNNEs5tva5MEICe0WoutKo3hF+l1kRtCY/GK+74wWrvi9Hjs9yD7PqK8cQCzXeW5bm5DF0uMts75xRRyAz3s= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CH3PR12MB8659.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(7416014)(366016)(1800799024)(921020); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /4u/bo3JWd4ng6NGvpuWp1gbKX5koInL6Z/KWS17EpxXMVnEU25NuwuKOOgYY3pGfyOR/kZ1CBdQUsk/irIJiXJwlxu3SBvrYu43TR4NUBEJPlM4kP8hel67QaZRb90kU/clH2QZl+rlhmPXN0gH0rH2+1Yit+DHRJgdvD2qoGXbvyG3f+vmHvkz19xt3BZbIh0xLhSWNrgBp5KXYEhf+/EWiIn2p1b0FM7tcjPQS7BuYAdkHomhBjFQZp8V6IID2iKp3RperX/pYdXkFBtmRkTw1eg6W9vYNLH3d5o8GtE3c8+pQvt96gdXRBVajKzKqommzmE/6tzT9u+lQzXijUiWQ4M/2M5mi/akiNT2jUDbt0qY0wdV1T4PggnqsHKQEKxNvArKVmWAcOW2A914IRr8A/EpUkQ0juZpHiyt0cWoCCaIRB3L5+4R2ORAKLhQJelMpSlz1c5HvkkCJAkYXdLNqkxFBTeDbv1/1dtUKcg7XCdKgEl3upkhH47n/ixbPsehhc5iZef7HUbwZ//6EMmeWxu6N19gEChEUImaJR2rS1oBVX7ESUBxAdb7NAFCH5qmWchtlQo5zZbVLMIRScqL5VjDqvMlA4thxjSGdUcaVeg/OhMpktNX6LwAPqiH48SwYvNvkWHkMRODKnU56xhLBzJp87xF8afpWlw5x/pkQD0lHe0eSZPY37MWPTPUkuCLvgoYUOnGAWbT38CFVtHJQDcgUS8G/yiAUvT7m00LBhIU0fP0EM6y1rI6Q+BL3QEAVv9Spo9pxsb83AqgNS2zBhtDaTS9OTIPu0OytGx4YZHmoT6/Es1q5ded1oB3/B0tcPqklxaOkMDAcyZG+GbjRbLm9h0FLoaKpUXRWAcWImTba3lLV2wpdH6dvMzShJEhrSP/oo4TeqRQBq5pHDKQQ/KaGcbm8RHeZ2658VVXsJF4MlGGLGCVSx/bm2/+vN7GBExU5L8o0ZO2Y81ADN7b4nyHfhW+oUvKk2gjCNdy7HTztD0iJyLZDhfq6tUap7M0sNwMG4x+W73Mi6jD5n3ZZrpOqlZoDAa27JGSzvyvNZ4U6y2p6rAubLs8TVu+cReV93Tv7AUMtBFFiq6Xl7aN+6v/2+i0TRLQ4CMCtig9lOEj8lyUCC6sSDPhJTUgfz+0knsWKQ2UF6qxSVd7N+R7LpB9Gi06JXXBoIgcIWLHd4b780+2kqCLiJ2a6iTdDrSgSObEa4uuHgvr5OGqj90CAJr8pZGiwAHRxx1uAGKOARJEXY+NpPFvuWaoqAnqvKxx6sStjKZMjyKZcrMOVF/CYz4VkA66oIrRusdIREAkpqlbgzJIG9YlirN7w8K8niuGg7OGcMUmK6CAt/nz345Uf06Vwu9AxmUqmyzUH+94hOYFIhRPSieJfrLIMBtESmi5JKO3sJWNFuUASKywriUmKGClA/Lk6BSNF4MVYMVFaecFB9Os5G1gqos0x7hnsDqkmzWX6WYNip6o/BvQFjhy7SKl+BRo+SFvZ0JteezWWYTRcPg1Qi9UDouiGnhLNeqf9ZMNlIfrl60R96iveMwsujuu0e9qEm0Td7RUy1g= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2163518a-4ab1-4c06-444d-08dcf941e402 X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 00:20:57.4980 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: c8yttwODnMWc4tz6Fu2Rda7svi4LuNhtqeOtDcOtw08rP6V2xv7vxZ3yv5fq7N6z X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7573 From: Nicolin Chen Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type. Implement an arm_vsmmu_alloc(). As an initial step, copy the VMID from s2_parent. A followup series is required to give the VIOMMU object it's own VMID that will be used in all nesting configurations. Signed-off-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 45 +++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 13 ++++++ include/uapi/linux/iommufd.h | 4 ++ 4 files changed, 63 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 3d2671031c9bb5..60dd9e90759571 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -29,3 +29,48 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) return info; } + +static const struct iommufd_viommu_ops arm_vsmmu_ops = { +}; + +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type) +{ + struct arm_smmu_device *smmu = + iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_domain *s2_parent = to_smmu_domain(parent); + struct arm_vsmmu *vsmmu; + + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return ERR_PTR(-EOPNOTSUPP); + + if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) + return ERR_PTR(-EOPNOTSUPP); + + if (s2_parent->smmu != master->smmu) + return ERR_PTR(-EINVAL); + + /* + * Must support some way to prevent the VM from bypassing the cache + * because VFIO currently does not do any cache maintenance. canwbs + * indicates the device is fully coherent and no cache maintenance is + * ever required, even for PCI No-Snoop. + */ + if (!arm_smmu_master_canwbs(master)) + return ERR_PTR(-EOPNOTSUPP); + + vsmmu = iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, + &arm_vsmmu_ops); + if (IS_ERR(vsmmu)) + return ERR_CAST(vsmmu); + + vsmmu->smmu = smmu; + vsmmu->s2_parent = s2_parent; + /* FIXME Move VMID allocation from the S2 domain allocation to here */ + vsmmu->vmid = s2_parent->s2_cfg.vmid; + + return &vsmmu->core; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b4b03206afbf48..c425fb923eb3de 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3517,6 +3517,7 @@ static struct iommu_ops arm_smmu_ops = { .dev_disable_feat = arm_smmu_dev_disable_feature, .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, + .viommu_alloc = arm_vsmmu_alloc, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index c9e5290e995a64..3b8013afcec0de 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -976,10 +977,22 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) } #endif /* CONFIG_TEGRA241_CMDQV */ +struct arm_vsmmu { + struct iommufd_viommu core; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *s2_parent; + u16 vmid; +}; + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type); #else #define arm_smmu_hw_info NULL +#define arm_vsmmu_alloc NULL #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index b227ac16333fe1..27c5117db985b2 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -400,10 +400,12 @@ struct iommu_hwpt_vtd_s1 { * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE = 0, IOMMU_HWPT_DATA_VTD_S1 = 1, + IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, }; /** @@ -843,9 +845,11 @@ struct iommu_fault_alloc { /** * enum iommu_viommu_type - Virtual IOMMU Type * @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use + * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1, }; /**