From patchwork Mon Jun 6 06:20:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 1751 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:55:22 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs12134vdc; Sun, 5 Jun 2011 23:13:28 -0700 (PDT) Received: by 10.42.178.195 with SMTP id bn3mr7926121icb.504.1307340807674; Sun, 05 Jun 2011 23:13:27 -0700 (PDT) Received: from mail-pw0-f50.google.com (mail-pw0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id ln4si3201253icb.99.2011.06.05.23.13.27 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 05 Jun 2011 23:13:27 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by pwi3 with SMTP id 3so2174567pwi.37 for ; Sun, 05 Jun 2011 23:13:26 -0700 (PDT) Received: by 10.68.20.201 with SMTP id p9mr1819218pbe.327.1307340806802; Sun, 05 Jun 2011 23:13:26 -0700 (PDT) Received: from localhost.localdomain ([114.216.154.92]) by mx.google.com with ESMTPS id y2sm3447688pbi.67.2011.06.05.23.12.55 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 05 Jun 2011 23:13:26 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Cc: grant.likely@secretlab.ca, jamie@jamieiles.com, kernel@pengutronix.de, patches@linaro.org, Shawn Guo Subject: [PATCH 2/2] gpio/mxs: convert gpio-mxs to use basic_mmio_gpio library Date: Mon, 6 Jun 2011 14:20:47 +0800 Message-Id: <1307341247-26382-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1307341247-26382-1-git-send-email-shawn.guo@linaro.org> References: <1307341247-26382-1-git-send-email-shawn.guo@linaro.org> The gpio-mxs controller complies with basic_mmio_gpio library. This patch converts the driver to use the library. Signed-off-by: Shawn Guo --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-mxs.c | 73 +++++++++-------------------------------------- 2 files changed, 15 insertions(+), 59 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index daaef0f..0b858e5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -96,6 +96,7 @@ config GPIO_EXYNOS4 config GPIO_MXS def_bool y depends on ARCH_MXS + select GPIO_BASIC_MMIO_CORE config GPIO_PLAT_SAMSUNG bool "Samsung SoCs GPIO library support" diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index d01f046..9897641 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #define MXS_SET 0x4 @@ -54,7 +55,7 @@ struct mxs_gpio_port { int irq; int irq_high; int virtual_irq_start; - struct gpio_chip chip; + struct bgpio_chip bgc; }; /* Note: This driver assumes 32 GPIOs are handled in one register */ @@ -99,8 +100,6 @@ static void mxs_gpio_unmask_irq(struct irq_data *d) set_gpio_irqenable(port, gpio & 0x1f, 1); } -static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); - static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) { u32 gpio = irq_to_gpio(d->irq); @@ -203,53 +202,6 @@ static struct irq_chip gpio_irq_chip = { .irq_set_wake = mxs_gpio_set_wake_irq, }; -static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, - int dir) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id); - - if (dir) - writel(1 << offset, pin_addr + MXS_SET); - else - writel(1 << offset, pin_addr + MXS_CLR); -} - -static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - - return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1; -} - -static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id); - - if (value) - writel(1 << offset, pin_addr + MXS_SET); - else - writel(1 << offset, pin_addr + MXS_CLR); -} - -static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - mxs_set_gpio_direction(chip, offset, 0); - return 0; -} - -static int mxs_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - mxs_gpio_set(chip, offset, value); - mxs_set_gpio_direction(chip, offset, 1); - return 0; -} - static int __devinit mxs_gpio_probe(struct platform_device *pdev) { static void __iomem *base; @@ -314,20 +266,23 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev) irq_set_chained_handler(port->irq, mxs_gpio_irq_handler); irq_set_handler_data(port->irq, port); - /* register gpio chip */ - port->chip.direction_input = mxs_gpio_direction_input; - port->chip.direction_output = mxs_gpio_direction_output; - port->chip.get = mxs_gpio_get; - port->chip.set = mxs_gpio_set; - port->chip.base = port->id * 32; - port->chip.ngpio = 32; - - err = gpiochip_add(&port->chip); + err = bgpio_init(&port->bgc, &pdev->dev, 4, + port->base + PINCTRL_DIN(port->id), + port->base + PINCTRL_DOUT(port->id), NULL, + port->base + PINCTRL_DOE(port->id), NULL, false); if (err) goto out_iounmap; + port->bgc.gc.base = port->id * 32; + + err = gpiochip_add(&port->bgc.gc); + if (err) + goto out_bgpio_remove; + return 0; +out_bgpio_remove: + bgpio_remove(&port->bgc); out_iounmap: if (iores) iounmap(port->base);