From patchwork Thu Sep 1 09:41:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3834 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 019AE23E52 for ; Thu, 1 Sep 2011 09:41:51 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id E5FD7A185AF for ; Thu, 1 Sep 2011 09:41:51 +0000 (UTC) Received: by fxd18 with SMTP id 18so753766fxd.11 for ; Thu, 01 Sep 2011 02:41:51 -0700 (PDT) Received: by 10.223.22.16 with SMTP id l16mr17666fab.62.1314870111690; Thu, 01 Sep 2011 02:41:51 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs45735lab; Thu, 1 Sep 2011 02:41:51 -0700 (PDT) Received: by 10.14.7.79 with SMTP id 55mr9186eeo.17.1314870110913; Thu, 01 Sep 2011 02:41:50 -0700 (PDT) Received: from eu1sys200aog105.obsmtp.com (eu1sys200aog105.obsmtp.com [207.126.144.119]) by mx.google.com with SMTP id e19si332377eeb.110.2011.09.01.02.41.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 01 Sep 2011 02:41:50 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.119 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.119; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.119 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKTl9TVrKefuSepNEvNU7KgmgCCWgDrGry@postini.com; Thu, 01 Sep 2011 09:41:50 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C045414A; Thu, 1 Sep 2011 09:41:39 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5A3B4104E; Thu, 1 Sep 2011 09:41:39 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 56E86A8096; Thu, 1 Sep 2011 11:41:34 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 1 Sep 2011 11:41:38 +0200 From: Linus Walleij To: Cc: Lee Jones , Linus Walleij , Srinidhi Kasagar , Rabin Vincent , Adrian Bunk Subject: [PATCH] mach-ux500: unlock I&D l2x0 caches before init Date: Thu, 1 Sep 2011 11:41:33 +0200 Message-ID: <1314870093-5758-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. This fixes a performance problem reported by Jan Rinze. Cc: Srinidhi Kasagar Cc: Rabin Vincent Cc: Adrian Bunk Reported-by: Jan Rinze Tested-by: Robert Marklund Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cache-l2x0.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 9d09e4d..96ef556 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -70,3 +70,18 @@ static int ux500_l2x0_init(void) } early_initcall(ux500_l2x0_init); + +static int ux500_l2x0_unlock(void) +{ + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. + */ + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_D) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); + + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_I) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); +} + +arch_initcall(ux500_l2x0_unlock);