From patchwork Mon Sep 26 07:20:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4325 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 898F223EFB for ; Mon, 26 Sep 2011 07:12:17 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 74A6DA18005 for ; Mon, 26 Sep 2011 07:12:17 +0000 (UTC) Received: by fxe23 with SMTP id 23so7940111fxe.11 for ; Mon, 26 Sep 2011 00:12:17 -0700 (PDT) Received: by 10.223.63.8 with SMTP id z8mr9998163fah.84.1317021137277; Mon, 26 Sep 2011 00:12:17 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.3.234 with SMTP id f10cs27673laf; Mon, 26 Sep 2011 00:12:17 -0700 (PDT) Received: by 10.52.75.9 with SMTP id y9mr5801957vdv.120.1317021135980; Mon, 26 Sep 2011 00:12:15 -0700 (PDT) Received: from TX2EHSOBE004.bigfish.com (tx2ehsobe002.messaging.microsoft.com. [65.55.88.12]) by mx.google.com with ESMTPS id g9si2430482vdw.69.2011.09.26.00.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 26 Sep 2011 00:12:15 -0700 (PDT) Received-SPF: neutral (google.com: 65.55.88.12 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=65.55.88.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.12 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: from mail134-tx2-R.bigfish.com (10.9.14.236) by TX2EHSOBE004.bigfish.com (10.9.40.24) with Microsoft SMTP Server id 14.1.225.22; Mon, 26 Sep 2011 07:12:14 +0000 Received: from mail134-tx2 (localhost.localdomain [127.0.0.1]) by mail134-tx2-R.bigfish.com (Postfix) with ESMTP id 9A74C16F0328; Mon, 26 Sep 2011 07:12:14 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail134-tx2 (localhost.localdomain [127.0.0.1]) by mail134-tx2 (MessageSwitch) id 1317021098550072_7857; Mon, 26 Sep 2011 07:11:38 +0000 (UTC) Received: from TX2EHSMHS037.bigfish.com (unknown [10.9.14.253]) by mail134-tx2.bigfish.com (Postfix) with ESMTP id 7335F8A004F; Mon, 26 Sep 2011 07:11:38 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS037.bigfish.com (10.9.99.137) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 26 Sep 2011 07:11:37 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.7; Mon, 26 Sep 2011 02:11:37 -0500 Received: from S2100-06.ap.freescale.net (S2100-06.ap.freescale.net [10.192.242.125]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p8Q7BPwN026498; Mon, 26 Sep 2011 02:11:35 -0500 (CDT) From: Shawn Guo To: Arnd Bergmann , Sascha Hauer CC: , , Shawn Guo Subject: [PATCH v3 4/6] arm/imx6q: add smp and cpu hotplug support Date: Mon, 26 Sep 2011 15:20:49 +0800 Message-ID: <1317021651-17359-5-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1317021651-17359-1-git-send-email-shawn.guo@linaro.org> References: <1317021651-17359-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com It adds smp and cpu hotplug support for imx6q. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/Makefile | 4 ++ arch/arm/mach-imx/head-v7.S | 71 ++++++++++++++++++++++++++ arch/arm/mach-imx/hotplug.c | 44 ++++++++++++++++ arch/arm/mach-imx/localtimer.c | 35 +++++++++++++ arch/arm/mach-imx/platsmp.c | 85 +++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/common.h | 5 ++ 7 files changed, 245 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-imx/head-v7.S create mode 100644 arch/arm/mach-imx/hotplug.c create mode 100644 arch/arm/mach-imx/localtimer.c create mode 100644 arch/arm/mach-imx/platsmp.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index af73b3e..6ec758d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -623,6 +623,7 @@ config SOC_IMX6Q bool "i.MX6 Quad support" select ARM_GIC select CPU_V7 + select HAVE_ARM_SCU select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8c21fda..d46b2e7 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -66,4 +66,8 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o +obj-$(CONFIG_CPU_V7) += head-v7.o +obj-$(CONFIG_SMP) += platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S new file mode 100644 index 0000000..ede908b --- /dev/null +++ b/arch/arm/mach-imx/head-v7.S @@ -0,0 +1,71 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include + + .section ".text.head", "ax" + __CPUINIT + +/* + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp< +#include +#include + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + flush_cache_all(); + imx_enable_cpu(cpu, false); + cpu_do_idle(); + + /* We should never return from idle */ + panic("cpu %d unexpectedly exit from shutdown\n", cpu); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c new file mode 100644 index 0000000..3a16351 --- /dev/null +++ b/arch/arm/mach-imx/localtimer.c @@ -0,0 +1,35 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +/* + * Setup the local clock events for a CPU. + */ +int __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); + if (!twd_base) { + twd_base = of_iomap(np, 0); + WARN_ON(!twd_base); + } + evt->irq = irq_of_parse_and_map(np, 0); + twd_timer_setup(evt); + + return 0; +} diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c new file mode 100644 index 0000000..ab98c6f --- /dev/null +++ b/arch/arm/mach-imx/platsmp.c @@ -0,0 +1,85 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void __iomem *scu_base; + +static struct map_desc scu_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_4K, + .type = MT_DEVICE, +}; + +void __init imx_scu_map_io(void) +{ + unsigned long base; + + /* Get SCU base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); + + scu_io_desc.virtual = IMX_IO_P2V(base); + scu_io_desc.pfn = __phys_to_pfn(base); + iotable_init(&scu_io_desc, 1); + + scu_base = IMX_IO_ADDRESS(base); +} + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + imx_set_cpu_jump(cpu, v7_secondary_startup); + imx_enable_cpu(cpu, true); + return 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + int i, ncores; + + ncores = scu_get_core_count(scu_base); + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); +} + +void imx_smp_prepare(void) +{ + scu_enable(scu_base); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + imx_smp_prepare(); +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 49cad2a..5b24f5d 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -88,4 +88,9 @@ void gic_handle_irq(struct pt_regs *); #define mx53_handle_irq tzic_handle_irq #define imx6q_handle_irq gic_handle_irq +extern void imx_enable_cpu(int cpu, bool enable); +extern void imx_set_cpu_jump(int cpu, void *jump_addr); +#ifdef CONFIG_SMP +extern void v7_secondary_startup(void); +#endif #endif